rggen
gf180mcu-pdk
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| rggen | gf180mcu-pdk | |
|---|---|---|
| 3 | 2 | |
| 277 | 335 | |
| 4.3% | 3.9% | |
| 7.7 | 2.8 | |
| 2 months ago | 11 months ago | |
| Ruby | Makefile | |
| MIT License | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
rggen
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RgGen v0.28.0
I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
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RgGen update (support C header file generation)
RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
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RgGen update
I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0
gf180mcu-pdk
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Exploded view of my first ASIC, inside the TinyTapeout project
Google just committed to open sourcing the SKY90FD (formerly MITLL's 90nm FDSOI) and GF180MCU processes as well. So there's growing momentum in the open source PDK space.
- GlobalFoundries GF180MCU Open Source PDK
What are some alternatives?
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
chipignite-resources
PeakRDL-ipxact - Import and export IP-XACT XML register models
sky90fd-pdk
edalize - An abstraction library for interfacing EDA tools
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4