qtrvsim
cs2410
| qtrvsim | cs2410 | |
|---|---|---|
| 1 | 1 | |
| 412 | 3 | |
| 4.1% | - | |
| 8.9 | 6.5 | |
| 5 days ago | 11 months ago | |
| C++ | C++ | |
| GNU General Public License v3.0 only | - |
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qtrvsim
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How a CPU works: Bare metal C on my RISC-V toy CPU
- source & native releases: https://github.com/cvut/qtrvsim
It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.
I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu
cs2410
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Sophie Wilson. She designed the architecture behind your phone’s CPU. She is also a trans woman.
Here is a CPU simulator that I made during the Spring semester, which implements a subset of the RISC V ISA. :)
What are some alternatives?
Astro8-Computer - Custom 16-bit homebrew CPU, emulator, renderer, circuit, and language
gem5 - The official repository for the gem5 computer-system architecture simulator.
Kite - Kite: Architecture Simulator for RISC-V Instruction Set
ChampSim - ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.
fpga-experiments
risc-v_pipelined_cpu - RISC-V CPU with a 5-stage pipeline, written in SystemVerilog
Digital - A digital logic designer and circuit simulator.
Ripes - A graphical processor simulator and assembly editor for the RISC-V ISA