How a CPU works: Bare metal C on my RISC-V toy CPU

• Digital

  85 4,276 7.1 Java

  A digital logic designer and circuit simulator.

  I have been building a CPU using: https://github.com/hneemann/Digital

  Much faster than Logisim, UI a little clunky, but my CPU runs around 0.5Mhz and it has very nice peripherals like Telnet, graphics ram, VGA etc

  Terrible name that is hard to google, but great tool.

• InfluxDB

  www.influxdata.com featured

  Purpose built for real-time analytics at any scale. InfluxDB Platform is powered by columnar analytics, optimized for cost-efficient storage, and built with open data standards.

  

• fpga-experiments

  1 8 10.0 Python

  You are right :)

  Here's the repo: https://github.com/fnoeding/fpga-experiments

  I'll update the post with it too.

• qtrvsim

  1 468 8.7 C++

  RISC-V CPU simulator for education purposes

  

  - source & native releases: https://github.com/cvut/qtrvsim

  It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.

  I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu

• risc-v_pipelined_cpu

  1 0 10.0 SystemVerilog

  RISC-V CPU with a 5-stage pipeline, written in SystemVerilog

  - source & native releases: https://github.com/cvut/qtrvsim

  It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.

  I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu

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