qtrvsim
Astro8-Computer
qtrvsim | Astro8-Computer | |
---|---|---|
1 | 2 | |
412 | 665 | |
4.1% | - | |
8.9 | 6.2 | |
5 days ago | about 2 months ago | |
C++ | C++ | |
GNU General Public License v3.0 only | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
qtrvsim
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How a CPU works: Bare metal C on my RISC-V toy CPU
- source & native releases: https://github.com/cvut/qtrvsim
It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.
I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu
Astro8-Computer
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Embedded Systems Weekly #112
I Designed My Own 16-bit CPU AstroSam, 16 years old, designed a 16-bit CPU called Astro-8, created an assembly language for it and finally created a compiled language named Armstrong (deal with it). All the video is entertaining and the work is impressive when you take into account Sam's age. All the code and schemas are on GitHub. I also discovered Logisim-evolution tool watching the video.
- I Designed My Own 16-Bit CPU
What are some alternatives?
Kite - Kite: Architecture Simulator for RISC-V Instruction Set
cpu_features - A cross platform C99 library to get cpu features at runtime.
fpga-experiments
logisim-evolution - Digital logic design tool and simulator
cs2410 - An out-of-order execution CPU simulator for CS2410 Computer Architecture course final project at the University of Pittsburgh.
Digital - A digital logic designer and circuit simulator.
risc-v_pipelined_cpu - RISC-V CPU with a 5-stage pipeline, written in SystemVerilog
Chimera - Automated DLL Sideloading Tool With EDR Evasion Capabilities
Ripes - A graphical processor simulator and assembly editor for the RISC-V ISA