qtrvsim
risc-v_pipelined_cpu
qtrvsim | risc-v_pipelined_cpu | |
---|---|---|
1 | 1 | |
412 | 0 | |
4.1% | - | |
8.9 | 10.0 | |
6 days ago | about 1 year ago | |
C++ | SystemVerilog | |
GNU General Public License v3.0 only | - |
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qtrvsim
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How a CPU works: Bare metal C on my RISC-V toy CPU
- source & native releases: https://github.com/cvut/qtrvsim
It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.
I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu
risc-v_pipelined_cpu
-
How a CPU works: Bare metal C on my RISC-V toy CPU
- source & native releases: https://github.com/cvut/qtrvsim
It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.
I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu
What are some alternatives?
Astro8-Computer - Custom 16-bit homebrew CPU, emulator, renderer, circuit, and language
fpga-experiments
Kite - Kite: Architecture Simulator for RISC-V Instruction Set
Digital - A digital logic designer and circuit simulator.
cs2410 - An out-of-order execution CPU simulator for CS2410 Computer Architecture course final project at the University of Pittsburgh.
Ripes - A graphical processor simulator and assembly editor for the RISC-V ISA