pyxsi
verilog-ethernet
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pyxsi | verilog-ethernet | |
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4 | 32 | |
54 | 1,916 | |
- | - | |
4.4 | 8.8 | |
5 months ago | about 2 months ago | |
C++ | Verilog | |
GNU General Public License v3.0 or later | MIT License |
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pyxsi
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Question for those who do DSP/algorithm verification
These three environments are glued together using pyxsi, which embeds Xilinx's simulator kernel (xsim). The result is a complicated monolith, but avoids the following "Bad Practices for Complex Dataflow":
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interaction between vivado simulator and C/C++
Adam mentions it in his Aduvio post, but pyxsi shows how to stack Python on C/C++ on Vivado. (Disclaimer: mine.)
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[CocoTB for beginners]: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub​
The sketch here is a little stale but shows the general idea.
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How good is the Vivado XSI?
I'm trying to understand if we can use the Vivado XSI to make our verification tasks easier and improve our coverage via a more productive language like C++ or python. I found an interesting project (https://github.com/gsmecher/pyxsi) that uses it but I'm still unsure if this is worth investing time on (given how many issues Xilinx tools usually have).
verilog-ethernet
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Quartus Tcl Build Script
Tcl, not sure, but I have done it with makefiles. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/C10LP/fpga.
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Using Si5324 as a clock generator on virtex-7 board
For that part I think you need to use the software from silicon labs (might be skyworks now) to generate the stuff you need to write to the registers. Then, you can use something like https://github.com/alexforencich/verilog-i2c/blob/master/rtl/i2c_init.v. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/HTG9200/fpga_10g for an example that targets the Si5341 specifically.
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DE2-115 Ethernet Network Setup
For a personal project I'm trying to send data via Ethernet from my laptop into the FPGA, where it has some filtering and other processing done to it, then back into my laptop. I've been trying to get this repo to work, but there's a problem: my ancient macbook can't run Quartus, so I need to use campus PCs to build the project and program the board, but I don't have permissions to successfully run the makefiles that build the project.
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ROS 2 Humble in AMD KR260 with Yocto
No there's none. Not in this post at least, but it certain is being used. If you're interested in that, follow my progress at https://github.com/alexforencich/verilog-ethernet/issues/146 (or stay tuned/reach out to Acceleration Robotics for early previews and support) for a 10G NIC on the KR260.
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Choice of LFSR When implementing the ARP Cache in a UDP Stack
So, im trying to understand the UDP implementation in verilog-ethernet. In particular I am looking into the ARP Cache and have a query.
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Preference for Combinational or Sequential design?
I've been studying u/alexforencich's ethernet library since I'm working on a similar project. I've been noting his interesting design style. When I think about a solution for a problem, I immediately naturally thing about a sequential design whereas he has tons of combination logic in his designs.
- Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
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Verilog Question- Setting a register concurrently twice in always block
I was studying Alex Forencich's FCS verilog and noticed the following always block:
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LiteX SGMII support
This repo support the VCU108 for a Verilog ethernet connection: https://github.com/alexforencich/verilog-ethernet
- Stream data into FPGA from PC
What are some alternatives?
rohd - The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
corundum - Open source FPGA-based NIC and platform for in-network compute
VHDL_real_time_simulation - Simple project for for a blog post with synthesizable models of buck converters
litex - Build your hardware, easily!
cocotbext-axi - AXI interface modules for Cocotb
SpinalHDL - Scala based HDL
embox - Modular and configurable OS for embedded applications
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
verilog-wishbone - Verilog wishbone components
liteeth - Small footprint and configurable Ethernet core
BYU_PYNQ_PR_Video_Pipeline_Hardware - BYU Pynq PR Video Pipeline Hardware