neorv32-riscof
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility. (by stnolting)
neorv32-setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains. (by stnolting)
| neorv32-riscof | neorv32-setups | |
|---|---|---|
| 2 | 5 | |
| 24 | 53 | |
| - | - | |
| 9.1 | 8.6 | |
| 6 days ago | 8 days ago | |
| Python | VHDL | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
neorv32-riscof
Posts with mentions or reviews of neorv32-riscof.
We have used some of these posts to build our list of alternatives
and similar projects.
neorv32-setups
Posts with mentions or reviews of neorv32-setups.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-20.
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How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG?
Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.
- RISC-V with AXI Peripheral
- Open-source RISC-V CPU projects for contribution
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A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs
and by "all" you of course mean some small Cyclones, Lattice ICE40s and Artix7 (see here)
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Risc-v rv32i softcore processor for Zybo-z7-10
There are some example setups here: https://github.com/stnolting/neorv32-setups
What are some alternatives?
When comparing neorv32-riscof and neorv32-setups you can also consider the following projects:
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU