libriscv VS sail-riscv

Seeking: https://github.com/fwsGonzo/libriscv

This is a C++ RISC-V emulator that focuses on isolating a single process, aka userspace emulation. I am currently working mostly on binary translation, and recently I have made a push to move it from experimental state to fully supported. Another experimental feature is embedding libtcc and using that for binary translation. It is fairly fast to compile, and gives decent speedups. The challenge is what to do now that (perhaps) some low hanging fruits have been picked.

I definitely recommend people to consider the base ISA of RISC-V if they want to try to implement a CPU or even full-system emulation. I understand that implementing a GameBoy emulator might be more attractive because you are working towards something graphical, but you can definitely get something similar with RISC-V, eg. Doom (SDL example: https://github.com/fwsGonzo/libriscv/tree/master/examples/do...)

This is the example project: https://github.com/fwsGonzo/libriscv/tree/master/examples/msvc

Pretty much two days of work: https://github.com/fwsGonzo/libriscv/commits/master

Show HN: Libriscv – RISC-V userspace emulator library\ (7 comments)

There is a doom emulation demo here now: https://github.com/fwsGonzo/libriscv/tree/master/emulator/do...

You will need to add the shareware doom1.wad yourself. :)

The official formal specification of the Vector Extension has just been merged into the Golden RISC-V model:

https://github.com/riscv/sail-riscv/commit/c90cf2e6eff5fa4ef...

the retired instruction counters when written by software.

Funnily enough the Sail model had this bug too! https://github.com/riscv/sail-riscv/issues/256

> loose specification of the RISC-V ISA.

This is being worked on with the Sail model [1]. In order for a RISC-V extension to be ratified it ought to be implemented in Sail. The understanding is also that the RISC-V ISA manual should be built with code snippets from the Sail model (similar to how the Arm Arm is build from ASL definition). The main issue is a lack of people willing and able to write Sail for RISC-V. But that is beginning to change, since RISC-V member companies are increasingly use Sail. As an example, the RISC-V exception type is defined in [2]. Is that precise enough for you?

[1] https://github.com/riscv/sail-riscv

[2] https://github.com/riscv/sail-riscv/blob/master/model/riscv_...

>it allows to formally verify the correctness of a particular ISA

That must be hypothetical. Functionalness of the language doesn't make anything that is written in it automatically subject to formal verification. (mechanized or pen and paper). What kind of correctness properties does it actually allow to formally verify? I understand if it was the F* language, which is a full blown dependently typed proof checker, but with F#, which is defined by the implementation and 300 page English spec, I don't think you can verify anything interesting. As far as I know F# itself doesn't have mechanized formal semantics and its type system could be unsound.

https://github.com/mit-plv/riscv-coq and https://github.com/riscv/sail-riscv (don't know how complete they are) approaches actually allow to formally (mechanically) verify riscv properties.

I guess you will also use Spike and the Sail model for RISC-V.

Doing something leveraging the SAIL model would be valuable, as that's the official formal model: https://github.com/rems-project/sail-riscv