jailhouse
riscv-isa-sim
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jailhouse | riscv-isa-sim | |
---|---|---|
3 | 15 | |
1,668 | 2,191 | |
0.5% | 3.7% | |
0.0 | 9.0 | |
about 1 year ago | 3 days ago | |
C | C | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
jailhouse
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Is there a way to run RISCV sim spike on bare metal?
You could run it inside something like jailhouse hypervisor (https://github.com/siemens/jailhouse) if you want to give it direct dedicated "baremetal" access to hardware. You could do this inside of a buildroot linux image. This would need a customized simulator.
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Nano98: Windows 98 that boots and runs under 5MB
Yes indeed, and Siemens even has their own hypervisor: https://github.com/siemens/jailhouse
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Rust for realtime motion control.
Yeah, I think that is what something like https://www.toradex.com/computer-on-modules/apalis-arm-family/nxp-imx-8 is useful for, where it has a separate core. Or even on linux you can use isolcpus to get pseudo-isolation. There are also hardware hypervisors like Jailhouse (https://github.com/siemens/jailhouse) which can completely isolate hardware resources and I suppose might prevent the GPU from causing an issue with realtime task. But this definitely affects ease-of-use and probably requires a reduced feature set in the language (no dynamic allocations) and lots of unsafe code.
riscv-isa-sim
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RISC-V simulator
Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.
- Help needed in building cavatools
- GCC 13 Adds RISC-V T-Head Vendor Extension Collection
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Hardware/software to run RISC-V ASM?
Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim
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most underrated cpp project you’ve seen?
I really like the source code for the Spike RISC-V ISA Simulator. It's not very heavily commented, though, so you really need to read the code.
- C++17 RISC-V RV32/64/128 userspace emulator library
- Buying RISC-V development board
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Is there a way to run RISCV sim spike on bare metal?
If you want to run bare metal with no RTOS, it should be possible, but you will need to replace the main startup program (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/spike_main/spike.cc) with some program to set up the hardware and instantiate the simulator, load the OS image etc and then have a decent runtime environment to that supports malloc() etc and redirect IO to serial or flash memory etc. There is a bit of work you would need to do.
- switching between privilege levels
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Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
What are some alternatives?
linux-embedded-hal - Implementation of the `embedded-hal` traits for Linux devices
riscv-arch-test
embedded-trainings-2020
sail-riscv - Sail RISC-V model
ethercat - Rust wrapper for the IgH EtherCAT master
rvv-intrinsic-doc
buildroot - Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
nanoCH32V305
wiser - :racehorse: Extremely minimal vmm for linux written in C. Hopefully someday will spin linux-vm for you.
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
Hypervisor-From-Scratch - Source code of a multiple series of tutorials about the hypervisor. Available at: https://rayanfam.com/tutorials
qemu