hVHDL_example_project
ruckus
| hVHDL_example_project | ruckus | |
|---|---|---|
| 10 | 2 | |
| 20 | 63 | |
| - | - | |
| 8.9 | 7.3 | |
| about 2 months ago | 12 days ago | |
| VHDL | Tcl | |
| MIT License | GNU General Public License v3.0 or later |
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hVHDL_example_project
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Designing with Lattice Diamond
https://github.com/hVHDL/hVHDL_example_project for instructions how to build it from tcl script
- Vivado Project vs Non-Project Mode
- A couple of questions for the experts
- Due to the supply chain issue I want to migrate from Xilinx Artix 7 to Efinix
- Changing dev flow from GUI to command line / scripting ?
- Folks who work as full time FPGA engineers, do you ever write any object oriented code?
- Choice of Python HDL library
- Create a common bus between multiple components in VHDL
- Present day analogues for Handel C / Impulse C?
ruckus
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Changing dev flow from GUI to command line / scripting ?
ruckus is makefile based https://github.com/slaclab/ruckus/blob/main/vivado/build.tcl
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Is it just me/my company or do FPGA tools and workflows suck at common software development practices like collaboration and CI/CD?
https://github.com/slaclab/ruckus is a makefile/tcl based approach.
What are some alternatives?
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
hVHDL_floating_point - high level VHDL floating point library for synthesis in fpga
migen - A Python toolbox for building complex digital hardware
magma - magma circuits
PipelineC - A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
litex - Build your hardware, easily!
rohd - The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
myhdl - The MyHDL development repository
hVHDL_fixed_point - VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and abc to dq transforms.
TDP-11
hVHDL_fpga_interconnect - interconnecting bus written in VHDL for accessing data in FPGA modules
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog