ghdl
VHDL 2008/93/87 simulator (by ghdl)
viv-prj-gen
tcl scripts used to build or generate vivado projects automatically (by TripRichert)
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| ghdl | viv-prj-gen | |
|---|---|---|
| 26 | 8 | |
| 2,210 | 21 | |
| 2.9% | - | |
| 9.8 | 1.9 | |
| 8 days ago | 10 months ago | |
| VHDL | CMake | |
| GNU General Public License v3.0 only | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ghdl
Posts with mentions or reviews of ghdl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-30.
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GHDL on mac m1
I downloaded https://github.com/ghdl/ghdl/releases/download/v3.0.0/ghdl-macos-11-mcode.tgz and extracted it to home directory ~.
- How to compile ghdl
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Is the VHDL standard library not publicly available?
The body is here.
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Help on trying to find a FOSS solution to replace Quartus in my class.
GHDL + gtkwave
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If someone is good at programming languages like C, will they be good at description languages like VHDL?
Also, VHDL has its roots in Ada, not Pascal. (In fact, the ghdl simulation tool is written in Ada.)
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What is the netlist file format?
If the goal is simulation, the output of the process is something that can be processed by a standard compiler (like gcc or llvm) or executed by a pseudocode interpreter. See, for example, what is done by ghdl.
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Converting VHDL to Verilog using GHDL
Maybe you could try to minimize your example to a MWE (minimum working example that demonstrates the issue) and then do a bug report against GHDL at https://github.com/ghdl/ghdl/issues
Try a question here: https://github.com/ghdl/ghdl/issues . I have only used GHDL for VHDL, and it worked well for what I was doing with it, but the creator/chief maintainer(?) (Tristan Gingold) should be able to set your issue straight in a short while, and he is pretty active on github.
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Trouble with GHDL and GCC
Find something newer here.
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ghdl, how to include math_real?
replying to myself: I just installed this nightly on a Win10 box and it seems to "work" based on minimal tests. Note that you need to install MinGW.
viv-prj-gen
Posts with mentions or reviews of viv-prj-gen.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-05-11.
- CI/CD for FPGA builds
- Vivado 2020.2 IP Repository Suggestion
- Comments and rants about tools, and a crazy idea
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Is it just me/my company or do FPGA tools and workflows suck at common software development practices like collaboration and CI/CD?
I wrote a similar cmake based project https://github.com/TripRichert/viv-prj-gen . It is no longer maintained (I wrote it as a personal project, but don't think I ever got any users for it, and can't contribute to it from work). But, It has got a tutorial https://github.com/TripRichert/viv-prj-gen/blob/master/tutorial/Tutorial.adoc , so you could check it out and see an automated workflow that I think is easy to get started with. This might give you some ideas how things could work.
- How do you manage your Vivado projects in git?
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Industry development process?
here's my script that does something similar https://github.com/TripRichert/viv-prj-gen/blob/master/tcl/gen_xactip.tcl
- What scripting languages are used in your job to help automate the design flow?
What are some alternatives?
When comparing ghdl and viv-prj-gen you can also consider the following projects:
logisim-evolution - Digital logic design tool and simulator
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
rust_hdl
Vivado_NonProjectMode_Example - An Basic Example and outline of the Vivado non Project mode Workflow
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
corundum - Open source FPGA-based NIC and platform for in-network compute
awesome-ada - A curated list of awesome resources related to the Ada and SPARK programming language
Documentation - OSVVM Documentation
gtkwave - GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
VHDL-Guide - VHDL Guide
hdl - HDL libraries and projects