freepdk-45nm
openlane
freepdk-45nm | openlane | |
---|---|---|
1 | 12 | |
108 | 1,179 | |
0.0% | 2.6% | |
10.0 | 8.4 | |
about 4 years ago | 9 days ago | |
Verilog | Python | |
- | Apache License 2.0 |
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freepdk-45nm
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Compiling Code into Silicon
Pretty neat, a python tool that converts Verilog to an IC layout so that you can make your own custom SOC (assuming you have a substantial budget to pay for fab).
Since it's not clearly stated on the front page, I had to go digging to figure out what processes it supports. Looks like FreePDK45, which is "an open-source generic process design kit (PDK) (i.e., does not correspond to any real process and cannot be fabricated)" [0], ASAP7 "Warning Work in progress (not ready for use)" [1] and Skywater130 which "As of May 2020, this repository is targeting the SKY130 process node. If the SKY130 process node release is successful then in the future more advanced technology nodes may become available." [2] The floorplanner supports their ZeroSOC [3] which I guess is based on TitanSOC [4]
If this sounds negative, it's not, I just couldn't figure out what processes this was intended for without digging. ASAP7 is Arm and NCSU, and Skywater130 is Skywater and Google.
[0] https://github.com/mflowgen/freepdk-45nm
openlane
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[D][P] Represent Analog Circuits as Graphs
I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.
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how small team survive from cadence cost
There are open source alternatives. https://github.com/The-OpenROAD-Project/OpenLane
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VLSI Tools
OpenLane
- Compiling Code into Silicon
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Kickstarting IC design
And, there is a project called 'The OpenROAD Project' which has created an open-source framework for digital back-end design/physical design. https://github.com/The-OpenROAD-Project/OpenLane
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How are modern processors and their architecture designed?
For "how the architecture is brought to silicon": Look at OpenLane. It's a complete Verilog to GDS flow, all open source and already used for some tape-outs. https://github.com/The-OpenROAD-Project/OpenLane
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Project Ideas for Uni
Maybe you can do something that can also go to an ASIC. Take a look at openlane flow, you don't need to do the backend since it is mostly script based and you can even send it to next Skywater submission. The major problem is that you currently don't have sram access so you need to create rams from logic if you need to.
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ASIC design post layout for padding.
I am not sure if you can do padding with this but dropping this down in case you haven't heard it: https://github.com/The-OpenROAD-Project/OpenLane
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Resources for a physical design engineer
Specifically openlane (https://github.com/The-OpenROAD-Project/OpenLane is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter
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Intro into chip design
https://github.com/efabless/openlane The README is very helpful
What are some alternatives?
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
edalize - An abstraction library for interfacing EDA tools
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
Verilog.jl - Verilog for Julia
rocket-chip - Rocket Chip Generator
opentitan - OpenTitan: Open source silicon root of trust
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
chisel - Chisel: A Modern Hardware Design Language
riscv - RISC-V CPU Core (RV32IM)
zerosoc - Demo SoC for SiliconCompiler.