fpga-docker
neorv32-setups
| fpga-docker | neorv32-setups | |
|---|---|---|
| 2 | 5 | |
| 66 | 56 | |
| - | - | |
| 0.0 | 8.6 | |
| about 1 year ago | 6 days ago | |
| Makefile | VHDL | |
| - | BSD 3-clause "New" or "Revised" License |
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fpga-docker
- Anyone try Docker desktop with FPGA tools env setup?
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Recommended CAD tools
This may not be what you are looking for, but instead of fiddling with installation on Ubuntu, I tried the fpga-docker, and it seems to work fine. Actually, because I decided to use Podman instead of Docker, I had to tinker a bit with file/directory permissions for the "home" directory that is created on the host's filesystem, but if you stick with Docker it will likely work out-of-the-box. After creating the udev file(on the Ubuntu host) programming from Quartus is working fine-ish[1]. The NativeLink(or whatever it's called) between Quartus and ModelSim doesn't work for some reason, so for now I'm using ModelSim as a standalone application.
neorv32-setups
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How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG?
Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.
- RISC-V with AXI Peripheral
- Open-source RISC-V CPU projects for contribution
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A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs
and by "all" you of course mean some small Cyclones, Lattice ICE40s and Artix7 (see here)
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Risc-v rv32i softcore processor for Zybo-z7-10
There are some example setups here: https://github.com/stnolting/neorv32-setups
What are some alternatives?
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
BrianHG-DDR3-Controller - DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
litex - Build your hardware, easily!
hdmi - Send video/audio over HDMI on an FPGA
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
neorv32 - :desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
fpu - IEEE 754 floating point library in system-verilog and vhdl
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
ORCA-risc-v - RISC-V by VectorBlox
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation