forth-cpu
sdram-fpga
forth-cpu | sdram-fpga | |
---|---|---|
2 | 2 | |
315 | 105 | |
- | - | |
2.6 | 10.0 | |
about 2 years ago | over 2 years ago | |
VHDL | VHDL | |
- | MIT License |
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forth-cpu
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Designs targeting specific boards?
Like in my head I thought having a piece of verilog and having enough LUTs in any board would do the thing, so what meant here? An example https://github.com/howerj/forth-cpu mentions that the target board is a specific Xilinx.
- Forth SoC Written in VHDL
sdram-fpga
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Seeking Help with SDRAM Controller Debugging
Initially, I attempted to adapt an SDRAM [controller project I found on GitHub]( https://github.com/nullobject/sdram-fpga/blob/master/sdram.vhd) to my board by configuring the necessary parameters such as timing constants and memory dimensions.
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SDRAM clock vs controller clock vs system clock
here you go
What are some alternatives?
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
uart-for-fpga - Simple UART controller for FPGA written in VHDL
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
fpga-toolchain - Multi-platform nightly builds of open source FPGA tools
Hastlayer-SDK - Turning .NET software into FPGA hardware for faster execution and lower power usage.
fpga-fft - A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
VHDL-Guide - VHDL Guide
wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).