corundum
Open source FPGA-based NIC and platform for in-network compute (by corundum)
viv-prj-gen
tcl scripts used to build or generate vivado projects automatically (by TripRichert)
| corundum | viv-prj-gen | |
|---|---|---|
| 28 | 8 | |
| 1,478 | 21 | |
| 2.7% | - | |
| 9.0 | 1.9 | |
| 7 days ago | 10 months ago | |
| Verilog | CMake | |
| GNU General Public License v3.0 or later | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
corundum
Posts with mentions or reviews of corundum.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-27.
-
FuryGpu – Custom PCIe FPGA GPU
The GPU uses this: https://github.com/alexforencich/verilog-pcie . And there is an open-source 100G NIC here, including open source 10G/25G MACs: https://github.com/corundum/corundum
- Open sourceCorundum – FPGA-based NIC and platform for in-network compute
- TCP checksum computation
- Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
-
xilinx versal gty testbench/data gen?
Well, I did build this: https://github.com/corundum/corundum
-
FPGA for finance industry
I would look into 10GbE PCS/MAC packet processors implemented under AXI Stream interfaces for example. There are open source examples https://github.com/corundum/corundum and https://netfpga.org/ .
-
Computer Networking Nerd and EE Student Looking to build a Baremetal Network Driver on top of baremetal kernel? Is this possible and if so, I'd like some guidance!
I built my own 100 Gbps capable NIC, along with driver: https://github.com/corundum/corundum. You're welcome to ask if you have any questions, though it is quite a different animal from a 100 Mbps NIC you might have on a microcontroller.
-
Device Drivers for Transceiver Questions (Specifically, PCIe)
If you're looking for resources, here's one rather comprehensive example of a high-performance FPGA design with a fully custom DMA engine and driver, that runs on both Xilinx and Intel FPGAs: https://github.com/corundum/corundum
-
shift/concatenate in v/sv
I have no idea, but you're welcome to build the design and look at it yourself: https://github.com/corundum/corundum/tree/master/fpga/mqnic/NetFPGA_SUME/fpga. The barrel shifters are in the DMA engine, both the read DMA and write DMA engines have wide barrel shifters.
-
Open source projects?
Dive right into the slack channel and introduce yourself. There is also a new contributor guide. /u/alexforencich/ is on these reddits and he may be able to chime in and give you more concrete suggestions.
viv-prj-gen
Posts with mentions or reviews of viv-prj-gen.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-05-11.
- CI/CD for FPGA builds
- Vivado 2020.2 IP Repository Suggestion
- Comments and rants about tools, and a crazy idea
-
Is it just me/my company or do FPGA tools and workflows suck at common software development practices like collaboration and CI/CD?
I wrote a similar cmake based project https://github.com/TripRichert/viv-prj-gen . It is no longer maintained (I wrote it as a personal project, but don't think I ever got any users for it, and can't contribute to it from work). But, It has got a tutorial https://github.com/TripRichert/viv-prj-gen/blob/master/tutorial/Tutorial.adoc , so you could check it out and see an automated workflow that I think is easy to get started with. This might give you some ideas how things could work.
- How do you manage your Vivado projects in git?
-
Industry development process?
here's my script that does something similar https://github.com/TripRichert/viv-prj-gen/blob/master/tcl/gen_xactip.tcl
- What scripting languages are used in your job to help automate the design flow?
What are some alternatives?
When comparing corundum and viv-prj-gen you can also consider the following projects:
verilog-ethernet - Verilog Ethernet components for FPGA implementation
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
rssguard - Feed reader (and podcast player) which supports RSS/ATOM/JSON and many web-based feed services.
Vivado_NonProjectMode_Example - An Basic Example and outline of the Vivado non Project mode Workflow
NvChad - Blazing fast Neovim config providing solid defaults and a beautiful UI, enhancing your neovim experience.
ghdl - VHDL 2008/93/87 simulator
litex - Build your hardware, easily!
Documentation - OSVVM Documentation
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
hdl - HDL libraries and projects
corundum vs verilog-ethernet
viv-prj-gen vs fusesoc
corundum vs rssguard
viv-prj-gen vs Vivado_NonProjectMode_Example
corundum vs NvChad
viv-prj-gen vs ghdl
corundum vs litex
viv-prj-gen vs Documentation
corundum vs soft_riscv
viv-prj-gen vs OsvvmLibraries
corundum vs psram-tang-nano-9k
viv-prj-gen vs hdl