cocotb
chisel-formal
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| cocotb | chisel-formal | |
|---|---|---|
| 28 | 1 | |
| 1,599 | 21 | |
| 4.1% | - | |
| 9.7 | 0.0 | |
| 7 days ago | about 3 years ago | |
| Python | Scala | |
| BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
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cocotb
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Designing a Low Latency 10G Ethernet Core
The use of cocotb and pyuvm for verification
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How is Python used in test automation in embedded systems?
For FPGA/HDL work, there's cocotb
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Introducing CoHDL
At the moment, it is not possible to directly simulate synthesizable contexts. In principle, I could add a simulator to CoHDL. As a Python implementation, it would be orders of magnitude slower than other solutions. Instead, I am using Cocotb to validate the generated VHDL and for the unit tests in the GitHub repository. There is also some very, very experimental support for formal verification, but it will take some time for that to become usable.
- Use cocotb to test and verify chip designs in Python
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Trying to learn and work with FPGAs
On the topic of simulation, you don't have to restrict yourself to using Verilog or VHDL to write your test benches. For example, Verilator lets you write them in C++, cocotb lets you use Python, and if you use SpinalHDL you will drive the underlying simulator using Scala.
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Help understanding how this makefile works?
I know it might be difficult without much context, but this makefile is called by a top level makefile. very confused if lines 35-74 do anything. They seem to be a mix of real makefile syntax and just straight up comments. what do these lines do?
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COBS protocol decoder progress
Learn more about this here: https://www.cocotb.org/
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AXI-Stream meme
Also consider cocotb, this thread has some compelling arguments. I'd say as a student, learning industry tools isn't necessarily the best thing you could spend your time on. Getting fast at design AND verification, where you can maintain flow state and run better microexperiments means you will understand more, faster.
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cocotb
Have you tried looking at the mixed language example?
- We're trying to sort this out with some of our engineers, so please humor - Do you prefer VHDL or Verilog?
chisel-formal
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What is the canonical way to test and simulate Chisel gateware ?
Formal (Yosys-smtbmc/chisel-formal): This is a really different approach to simulation with property checking. I first tryied it on generated verilog, then with chisel-formal module. This is a solution that is not yet mature for Chisel in my opinion.
What are some alternatives?
cocotbext-axi - AXI interface modules for Cocotb
cocotb-test - Unit testing for cocotb
amaranth - A modern hardware definition language and toolchain based on Python
chiselverify - A dynamic verification library for Chisel.
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
SpinalHDL - Scala based HDL
chisel - Chisel: A Modern Hardware Design Language
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
PipelineC - A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
hdl_checker - Repurposing existing HDL tools to help writing better code
circt - Circuit IR Compilers and Tools
verilog-axi - Verilog AXI components for FPGA implementation