Surelog
slang
| Surelog | slang | |
|---|---|---|
| 1 | 4 | |
| 330 | 535 | |
| 2.7% | - | |
| 9.4 | 9.7 | |
| 2 months ago | 7 days ago | |
| C++ | C++ | |
| Apache License 2.0 | MIT License |
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Surelog
slang
- Is anyone aware of a commercial parser that converts modern system verilog, UVM, etc to JSON or YAML?
- Tools like Scitools Understand but support Verilog
- What cli tool can give me a list of input/ouput pins of my verilog modules?
-
AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be Enabled by Xilinx Tech
Going to plug my work on this here: https://github.com/MikePopoloski/slang
At some point I'd like to see it integrated as the frontend to tools like Yosys to get best-in-class SystemVerilog support in open tools.
What are some alternatives?
verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
sleighcraft - sleigh craft!
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
naja-verilog - A standalone structural (gate-level) verilog parser
iverilog - Icarus Verilog
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
json - A C++11 library for parsing and serializing JSON to and from a DOM container in memory.
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
veridian - A SystemVerilog Language Server
quick-lint-js - quick-lint-js finds bugs in JavaScript programs
Diagon - Interactive ASCII art diagram generators. :star2: