blarney
rggen
| blarney | rggen | |
|---|---|---|
| 1 | 3 | |
| 89 | 280 | |
| - | 2.1% | |
| 7.1 | 7.7 | |
| 1 day ago | 3 months ago | |
| Haskell | Ruby | |
| GNU General Public License v3.0 or later | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
blarney
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Clash: A Functional Hardware Description Language
As described in my other comment, Clash is not like Chisel in that Clash compiles Haskell source code directly, while Chisel is an EDSL (in Scala)
Since you’re more familiar with Haskell, perhaps have a look at Blarney: https://github.com/blarney-lang/blarney/blob/master/Doc/ByEx...
rggen
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RgGen v0.28.0
I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
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RgGen update (support C header file generation)
RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
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RgGen update
I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0
What are some alternatives?
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
PeakRDL-ipxact - Import and export IP-XACT XML register models
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
edalize - An abstraction library for interfacing EDA tools
rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
veryl - Veryl: A Modern Hardware Description Language
gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
systemrdl-compiler - SystemRDL 2.0 language compiler front-end
rggen-verilog-rtl - Common Verilog RTL modules for RgGen
rggen-vhdl-rtl