bit-serial
A bit-serial CPU written in VHDL, with a simulator written in C. (by howerj)
mrisc32-a1
A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA (by mrisc32)
bit-serial | mrisc32-a1 | |
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1 | 3 | |
111 | 22 | |
- | - | |
6.7 | 0.0 | |
3 months ago | 9 months ago | |
VHDL | VHDL | |
MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
bit-serial
Posts with mentions or reviews of bit-serial.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-04-03.
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The ancient world before computers had stacks or heaps
I wrote a Forth interpreter for a SUBLEQ machine (https://github.com/howerj/subleq), and for a bit-serial machine (https://github.com/howerj/bit-serial), both of which do not have a function call stack which is a requirement of Forth. SUBLEQ also does not allow indirect loading and stores as well and requires self-modifying code to do anything non-trivial. The approach I took for both machines was to build a virtual machine that could do those things, along with cooperative multithreading. The heap, if required, is written in Forth, along with a floating point word-set (various MCUs not having instructions for floating point numbers is still fairly common, and can be implemented as calls to software functions that implement them instead).
I would imagine that other compilers took a similar approach which wasn't mentioned.
mrisc32-a1
Posts with mentions or reviews of mrisc32-a1.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-06-10.
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Got any good reads on floating point math design?
I saw a particularly efficient VHDL implementation in the mrisc32-a1, though this is lacking support for rounding modes. Together with the rest of the processor this is a very interesting project, I hope that the author progresses it further.
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Find the leading '0' Verilog question
Here is a different more logic gate:ish solution (in VHDL): https://github.com/mrisc32/mrisc32-a1/blob/master/rtl/alu/clz32.vhd
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Floating point unit in systemc
In my VHDL implementation I use the same iterative divider for integer and for floating-point: https://github.com/mrisc32/mrisc32-a1/blob/master/rtl/muldiv/div_impl.vhd
What are some alternatives?
When comparing bit-serial and mrisc32-a1 you can also consider the following projects:
cvfpu - Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
fpu-sp - IEEE 754 floating point library in system-verilog and vhdl
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
hlsVHDL_floating_point