apio
6502-exp
| apio | 6502-exp | |
|---|---|---|
| 3 | 1 | |
| 754 | 0 | |
| 1.7% | - | |
| 9.7 | 10.0 | |
| 5 days ago | about 3 years ago | |
| Verilog | Assembly | |
| GNU General Public License v3.0 only | - |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
apio
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Looking for help getting started with TinyFPGA
apio is a python package you drive from the command line. I didn't know somebody had done an integration with Atom. I've installed and used apio on my phone. I wouldn't really recommend doing that, but it shows what's possible.
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Learning Verilog and FPGA
I've had good experiences using Upduino 3.0 and 3.1 [0] with the IceStorm tools via apio [1]. I wrote a blog post [2] with some info on getting things set up via Linux. All you need is the Upduino board, which interfaces to your host system via USB (so no special programmer is needed).
[0] https://tinyvision.ai/products/upduino-v3-1
[1] https://github.com/FPGAwars/apio
[2] https://daveho.github.io/2021/02/07/upduino3-getting-started...
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FPGA dev board that's cheap, simple and supported by OSS toolchain
if you're more comfortable with the CLI, you should take a look at the apio project (https://github.com/FPGAwars/apio). It neatly bundles all the required tools. Regarding HDLs, I'm still learning so can't offer any good advice on that.
6502-exp
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Learning Verilog and FPGA
Chisel is compiled to Verilog so it has excellent interoperability. You can use Chisel in an existing Verilog project or use existing Verilog modules in a Chisel project. Therefore it is already supported by practically all vendors and simulators.
I've used Chisel to interface with proprietary Lattice DSPs and RAM modules, and I'm sure you could do the same with other vendors as well. All you have to do is define the IOs and parameters of the module. In Chisel this is called a "Blackbox". Example: https://github.com/fayalalebrun/6502-exp/blob/master/src/mai...
What are some alternatives?
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
prince - The Prince lightweight block cipher in Verilog.
UPduino-v3.0 - UPduino 3.0: new 4 layer layout, various other improvements
prjtrellis - Documenting the Lattice ECP5 bit-stream format.
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
icestudio - :snowflake: Visual editor for open FPGA boards
edalize - An abstraction library for interfacing EDA tools
fomu-toolchain - A collection of tools for developing for Fomu
nmigen-tutorial - A tutorial for using nmigen
openpiton - The OpenPiton Platform