ao486_MiSTer
SpinalHDL
ao486_MiSTer | SpinalHDL | |
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21 | 8 | |
236 | 1,523 | |
0.4% | 2.0% | |
5.8 | 9.8 | |
6 days ago | 4 days ago | |
Verilog | Scala | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
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ao486_MiSTer
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Reverse engineering the Intel 386 processor's register cell
How about a 486 instead? :)
https://github.com/MiSTer-devel/ao486_MiSTer
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Issues with AO486
Have you checked all the details in https://github.com/MiSTer-devel/ao486_MiSTer ?
- Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
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Recently, I came across a video on Youtube by Linus Tech Tips about the PCEm emulator that I found to be cringy and ill-informed. As a computer engineer by education let me explain few core concepts on how emulation works.
You mention "Pentium MMX CPU" a few times in your post, but fail to mention any FPGA solution that can emulate a machine of that class. MiSTer can't do that, the best it can do is a 486 (not just missing MMX, doesn't even have an FPU).
- Exact 486 CPU Performance in Smallest Form Factor
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Emulate Any ISA Card With A Raspberry Pi And An FPGA
It has already happened: https://github.com/MiSTer-devel/ao486_MiSTer
- Are there FPGA cores for SB16/ET4KW32/NE2K?
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KEYBCS2
The last processor generation it worked on is the 486, but on a Pentium or newer it always fails with a “Debugging is not allowed” message.
I guessed the reason for that correctly - prefetch queue. Mentions of CUP386 in the comments also brought back more memories of the cracking scene in the late 80s/early 90s. There's some very interesting discussion on SMC vs CPU behaviour here --- in the context of an open-source 486-level SoC core:
https://github.com/MiSTer-devel/ao486_MiSTer/issues/33
SpinalHDL
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1800-2023 – IEEE Standard for SystemVerilog
I'd love to see textual preprocessors kinda banned. Or at least done upstream and outside of the language. You can't both be and also have a textual preprocessor defined internally. It doesn't work.
I really like what Zig and C++ are doing with `const`.
https://ikrima.dev/dev-notes/zig/zig-metaprogramming/
Have you looked at Spinal?
https://github.com/SpinalHDL/SpinalHDL
https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html
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Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.
If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.
[1] https://github.com/ucb-bar/chipyard
[2] https://github.com/SpinalHDL/SpinalHDL
[3] https://github.com/B-Lang-org/bsc
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Simple skid buffer implementation
I have just found that SpinalHDL also implemented two halves of the fully registered buffer in Stream.scala.
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Why are there only 3 languages for FPGA development?
Don’t forget SpinalHDL that was forked off of Chisel 2 I believe. These DSLs really leveraged the software features of Scala to help build generalised/modular systems. And are generally a quality of life improvement in the language features available.
- SpinalHDL – A high level hardware description language based on Scala
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)
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Suggest advance project ideas
You could try to implement a PCIe root complex for FOSS SoCs, connecting to e.g. Wishbone as the main bus. There's already some DDR3 controller (or this one) and USB Host controller out there, and even device-side PCIe, but no FOSS host-side PCIe that I know of. Probably quite a difficult job though, even sticking to the lower-speed PCIe 1.
- Chisel/Firrtl Hardware Compiler Framework
What are some alternatives?
dosbox-x - DOSBox-X fork of the DOSBox project
chisel - Chisel: A Modern Hardware Design Language
PCem-ROMs - This is a collection of requiered ROMs files for PCem emulator. RIP PCem 2021
amaranth - A modern hardware definition language and toolchain based on Python
elks - Embeddable Linux Kernel Subset - Linux for 8086
litex - Build your hardware, easily!
libi86 - Attempt to reimplement non-standard C library facilities (e.g. <conio.h>) used in MS-DOS programs, for IA-16 GCC & ACK ― mirror of https://gitlab.com/tkchia/libi86 • Ubuntu packages for cross-compilation at https://launchpad.net/%7Etkchia/+archive/ubuntu/build-ia16/ • DJGPP/MS-DOS binaries at https://github.com/tkchia/libi86/releases
chiselverify - A dynamic verification library for Chisel.
NyuziProcessor - GPGPU microprocessor architecture
litepcie - Small footprint and configurable PCIe core
vISA
circt - Circuit IR Compilers and Tools