Vitis_Accel_Examples
Vitis-Tutorials
Vitis_Accel_Examples | Vitis-Tutorials | |
---|---|---|
3 | 4 | |
467 | 1,063 | |
1.5% | 2.6% | |
8.0 | 9.3 | |
4 months ago | 20 days ago | |
Makefile | C | |
MIT License | MIT License |
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Vitis_Accel_Examples
- Can you help me dataflow checking failure on vitis hls?
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How to Implement a decision tree on FPGA?
3- Then in Vitis I have implement that if-else statement to build the hardware. I have taken this Vitis hello world example as reference to write code for decision tree.
- Design AXI4 MM -> S and S -> MM
Vitis-Tutorials
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How to use maximum HBM bandwidth?
Currently, I am only reading/writing 64 bits with each access (code below). I found a sample code in the Xilinx repository (link) that utilizes all 512 bits of an AXI port, but I am struggling with how to use parallel AXI ports (32 ports). I would greatly appreciate any hints or guidance on this.
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Xilinx HLS AXI4-Lite registers don't update right away
Here is the top level function. It is a modified version of the convolution HLS provided in one of Xilinx's Vitis tutorials. I've run into a similar problem for other HLS IP where the AXI4-Lite registers don't update right away. ``` void Filter2DKernel( const float coeffs[MAX_COEFFS], float factor, short bias, unsigned short width, unsigned short height, unsigned short stride, hls::stream &input_stream, hls::stream &output_stream) {
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
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Xilinx expensive accelerate card
Here are some resources: 1. Vitis AI on Custom Platform 2. Vitis Platform Creation
What are some alternatives?
XRT - Run Time for AIE and FPGA based platforms
finn-examples - Dataflow QNN inference accelerator examples on FPGAs
hlslib - A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
red-pitaya-notes - Notes on the Red Pitaya Open Source Instrument
lfbb - A Lock Free Bipartite Buffer Library written in standard C11
Alveo-PYNQ - Introductory examples for using PYNQ with Alveo
o1heap - Constant-complexity deterministic memory allocator (heap) for hard real-time high-integrity embedded systems. There is very little activity because the project is finished and does not require further changes.
c8hardcaml - An implementation of a CHIP-8 machine for FPGAs in Hardcaml with a custom assembler for writing test programs
acap3-examples - Example code for APIs and features in AXIS Camera Application Platform (ACAP) version 3
Vitis-HLS-Introductory-Examples