Vitis_Accel_Examples
c8hardcaml
| Vitis_Accel_Examples | c8hardcaml | |
|---|---|---|
| 3 | 1 | |
| 467 | 8 | |
| 1.5% | - | |
| 8.0 | 0.0 | |
| 4 months ago | almost 2 years ago | |
| Makefile | OCaml | |
| MIT License | - |
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Vitis_Accel_Examples
- Can you help me dataflow checking failure on vitis hls?
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How to Implement a decision tree on FPGA?
3- Then in Vitis I have implement that if-else statement to build the hardware. I have taken this Vitis hello world example as reference to write code for decision tree.
- Design AXI4 MM -> S and S -> MM
c8hardcaml
What are some alternatives?
XRT - Run Time for AIE and FPGA based platforms
esp32_usb_soft_host - ESP32 software USB host through general IO pins. We can connect up to 4 USB-LS HID (keyboard mouse joystick) devices simultaneously.
hlslib - A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
em-dosbox - An Emscripten port of DOSBox
red-pitaya-notes - Notes on the Red Pitaya Open Source Instrument
Introduction-to-SoC-Design-Education-Kit - Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals
Vitis-Tutorials - Vitis In-Depth Tutorials
pixels - A tiny hardware-accelerated pixel frame buffer. 🦀
Alveo-PYNQ - Introductory examples for using PYNQ with Alveo
ppsspp - A PSP emulator for Android, Windows, Mac and Linux, written in C++. Want to contribute? Join us on Discord at https://discord.gg/5NJB6dD or just send pull requests / issues. For discussion use the forums at forums.ppsspp.org.
acap3-examples - Example code for APIs and features in AXIS Camera Application Platform (ACAP) version 3
PipelineC - A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.