Vitis_Accel_Examples VS Vitis-Tutorials

3- Then in Vitis I have implement that if-else statement to build the hardware. I have taken this Vitis hello world example as reference to write code for decision tree.

Currently, I am only reading/writing 64 bits with each access (code below). I found a sample code in the Xilinx repository (link) that utilizes all 512 bits of an AXI port, but I am struggling with how to use parallel AXI ports (32 ports). I would greatly appreciate any hints or guidance on this.

Here is the top level function. It is a modified version of the convolution HLS provided in one of Xilinx's Vitis tutorials. I've run into a similar problem for other HLS IP where the AXI4-Lite registers don't update right away. ``` void Filter2DKernel( const float coeffs[MAX_COEFFS], float factor, short bias, unsigned short width, unsigned short height, unsigned short stride, hls::stream &input_stream, hls::stream &output_stream) {

Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform

Here are some resources: 1. Vitis AI on Custom Platform 2. Vitis Platform Creation