Vitis-Tutorials
lfbb
Vitis-Tutorials | lfbb | |
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4 | 10 | |
1,068 | 56 | |
3.1% | - | |
9.3 | 6.2 | |
25 days ago | about 1 month ago | |
C | C++ | |
MIT License | MIT License |
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Vitis-Tutorials
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How to use maximum HBM bandwidth?
Currently, I am only reading/writing 64 bits with each access (code below). I found a sample code in the Xilinx repository (link) that utilizes all 512 bits of an AXI port, but I am struggling with how to use parallel AXI ports (32 ports). I would greatly appreciate any hints or guidance on this.
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Xilinx HLS AXI4-Lite registers don't update right away
Here is the top level function. It is a modified version of the convolution HLS provided in one of Xilinx's Vitis tutorials. I've run into a similar problem for other HLS IP where the AXI4-Lite registers don't update right away. ``` void Filter2DKernel( const float coeffs[MAX_COEFFS], float factor, short bias, unsigned short width, unsigned short height, unsigned short stride, hls::stream &input_stream, hls::stream &output_stream) {
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
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Xilinx expensive accelerate card
Here are some resources: 1. Vitis AI on Custom Platform 2. Vitis Platform Creation
lfbb
- A lock-free ring-buffer with contiguous reservations (2019)
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OpenPicoRTOS: 'cause the world DEFINITELY needs another RTOS !
If you're interested in how to do that you can check out a library of mine: https://github.com/DNedic/lfbb (although you don't need to bother with memory ordering if you don't want, you can just use the sequential consistency model).
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How do you handle data coupling between RTOS tasks?
You might be interested to take a look at this if efficiency is one of your goals: https://github.com/DNedic/lfbb
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Library for generic ringbuffer that can be filled via DMA?
I have exactly what you are looking for https://github.com/DNedic/lfbb
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Best practices on loosely coupling the high-level modules on a sensor-packager-transmitter embedded c device.
I don't see a reason SensorCollector should send a flag when there is enough data to send, the circular buffer object should be able to tell you when there is enough data to send and it should not be coupled to your specific applicaton. For situations where you want the data to always be contigous and need a general purpose circular buffer, you can take a look at a library i wrote: https://github.com/DNedic/lfbb
- LFBB – A Lock Free Bipartite Buffer Library Written in Standard C11
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Best practice for preventing data collisions between ISR and non ISR code without turning off interrupts? (FreeRTOS)
If you need something more advanced, check this out: https://github.com/DNedic/lfbb
- A Lock Free Bipartite Buffer Library Written in Standard C11
- Lock Free Bipartite Buffer Library Written in Standard C11
- A Lock Free Bipartite Buffer library written in standard C11
What are some alternatives?
finn-examples - Dataflow QNN inference accelerator examples on FPGAs
lwrb - Lightweight generic ring buffer manager library
hlslib - A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
nanoprintf - The smallest public printf implementation for its feature set.
o1heap - Constant-complexity deterministic memory allocator (heap) for hard real-time high-integrity embedded systems. There is very little activity because the project is finished and does not require further changes.
fifo_map - a FIFO-ordered associative container for C++
Alveo-PYNQ - Introductory examples for using PYNQ with Alveo
muon - GPU based Electron on a diet
Vitis-HLS-Introductory-Examples
OpenPicoRTOS - Very small, safe, lightning fast, yet portable preemptive RTOS with SMP support
Vitis_Accel_Examples - Vitis_Accel_Examples
fprime - F´ - A flight software and embedded systems framework