Vitis-Tutorials
Alveo-PYNQ
| Vitis-Tutorials | Alveo-PYNQ | |
|---|---|---|
| 4 | 1 | |
| 1,068 | 45 | |
| 3.1% | - | |
| 9.3 | 1.8 | |
| 25 days ago | about 1 year ago | |
| C | Jupyter Notebook | |
| MIT License | Apache License 2.0 |
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Vitis-Tutorials
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How to use maximum HBM bandwidth?
Currently, I am only reading/writing 64 bits with each access (code below). I found a sample code in the Xilinx repository (link) that utilizes all 512 bits of an AXI port, but I am struggling with how to use parallel AXI ports (32 ports). I would greatly appreciate any hints or guidance on this.
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Xilinx HLS AXI4-Lite registers don't update right away
Here is the top level function. It is a modified version of the convolution HLS provided in one of Xilinx's Vitis tutorials. I've run into a similar problem for other HLS IP where the AXI4-Lite registers don't update right away. ``` void Filter2DKernel( const float coeffs[MAX_COEFFS], float factor, short bias, unsigned short width, unsigned short height, unsigned short stride, hls::stream &input_stream, hls::stream &output_stream) {
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
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Xilinx expensive accelerate card
Here are some resources: 1. Vitis AI on Custom Platform 2. Vitis Platform Creation
Alveo-PYNQ
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How to Implement a decision tree on FPGA?
5- Use pynq library to run that binary file on the board. I have taken this pynq example as reference.
What are some alternatives?
finn-examples - Dataflow QNN inference accelerator examples on FPGAs
Vitis_Accel_Examples - Vitis_Accel_Examples
hlslib - A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
PYNQ - Python Productivity for ZYNQ
lfbb - A Lock Free Bipartite Buffer Library written in standard C11
rfsoc_studio - The Strathclyde RFSoC Studio Installer for PYNQ.
o1heap - Constant-complexity deterministic memory allocator (heap) for hard real-time high-integrity embedded systems. There is very little activity because the project is finished and does not require further changes.
Vitis-HLS-Introductory-Examples
rosetta - Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy