VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA (by hughperkins)
ulm-on-ice
ULM (Ulm Lecture Machine) on ice40 (by michael-lehn)
| VeriGPU | ulm-on-ice | |
|---|---|---|
| 2 | 1 | |
| 484 | 2 | |
| - | - | |
| 0.0 | 5.6 | |
| about 1 year ago | about 1 year ago | |
| SystemVerilog | SystemVerilog | |
| MIT License | GNU General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
VeriGPU
Posts with mentions or reviews of VeriGPU.
We have used some of these posts to build our list of alternatives
and similar projects.
ulm-on-ice
Posts with mentions or reviews of ulm-on-ice.
We have used some of these posts to build our list of alternatives
and similar projects.
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Building your own computer with an FPGA
I used a Lattice ice40 FPGA (e.g. icebreaker) FPGA to implement a simple RISC microprocessor. For the hardware description I used SystemVerilog and an open source toolchain. The source code is on GitHub.
What are some alternatives?
When comparing VeriGPU and ulm-on-ice you can also consider the following projects:
Cores-VeeR-EL2 - VeeR EL2 Core
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
riscv-simple-sv - A simple RISC V core for teaching
libsv - An open source, parameterized SystemVerilog digital hardware IP library
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
BrianHG-DDR3-Controller - DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Cores-VeeR-EH1 - VeeR EH1 core
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
clic - RISC-V fast interrupt controller