VeriGPU VS riscv-simple-sv

Compare VeriGPU vs riscv-simple-sv and see what are their differences.

VeriGPU

OpenSource GPU, in Verilog, loosely based on RISC-V ISA (by hughperkins)
Verilog risc-v risc-v-assembly hardware-designs asic-design GPU gpu-acceleration Machine Learning Verification
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riscv-simple-sv

A simple RISC V core for teaching (by tilk)
risc-v Riscv Verilog
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VeriGPU riscv-simple-sv
2 2
484 145
- -
0.0 0.0
about 1 year ago over 2 years ago
SystemVerilog SystemVerilog
MIT License BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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VeriGPU

Posts with mentions or reviews of VeriGPU. We have used some of these posts to build our list of alternatives and similar projects.

riscv-simple-sv

Posts with mentions or reviews of riscv-simple-sv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-04-10.
  • Simple CPU cores to study?
    3 projects | /r/Verilog | 10 Apr 2021
    I published the code on GitHub: https://github.com/tilk/riscv-simple-sv
  • Need help in CPU design
    5 projects | /r/FPGA | 22 Mar 2021
    I need to run a RISC-V softcore in my FPGA. I don't need to develop the core myself, which means I can use one with good support and that is well implemented (if someone knows a good one, tell me in the comments, please). Since I'm a little new to this area I started by using a simple core: https://github.com/tilk/riscv-simple-sv, however, I'm a little lost in the steps that I need to do. First, I need to put the core in my FPGA. Then, how can I execute code in the core? Do I need to put the machine code into the ROM? And how can I do that? What if I want to debug my C programs that are supposed to run on the core?

What are some alternatives?

When comparing VeriGPU and riscv-simple-sv you can also consider the following projects:

Cores-VeeR-EL2 - VeeR EL2 Core

cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Cores-VeeR-EH1 - VeeR EH1 core

gdb-stub - gdb-proxy implementation for bonfire

picoMIPS - picoMIPS processor doing affine transformation

VeriGPU vs Cores-VeeR-EL2 riscv-simple-sv vs cv32e40p VeriGPU vs ibex riscv-simple-sv vs scr1 VeriGPU vs Cores-VeeR-EH1 riscv-simple-sv vs gdb-stub VeriGPU vs scr1 riscv-simple-sv vs picoMIPS