VHDL-Issues
amaranth
VHDL-Issues | amaranth | |
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11 | 7 | |
- | 1,444 | |
- | 1.8% | |
- | 9.7 | |
- | 4 days ago | |
Python | ||
- | BSD 2-clause "Simplified" License |
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VHDL-Issues
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What would be your go-to solution for configurable number of entity's output signals? (VHDL)
Not possible until VHDL 2019 using conditional analysis (basically VHDL pre-processor). This is supported by the newest intel Pro tools and most paid for simulators. A better version, without having to use conditional analysis, is proposed for VHDL 202X : https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/205
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How to create a register array in VHDL in which each entry in the array has input and outputting on the same cycle, behaves as a register, and is coded as an entry in an array?
You are confusing all sorts of VHDL terms. my_array is simply an array object, it has no ports. Ports exist on an entity. Vhdl has no direct knowledge of underlying hardware, hence register_array would not be suitable as a VHDL keyword. If you think it is, you need to suggest it at https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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Why are there only 3 languages for FPGA development?
For those who would like to see additional features / simplifications in VHDL, the working group accepts issues at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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A new suggested keyword register_array for VHDL
Reddit is not really a great place to suggest language modifications. The vhdl committee have a gitlab issues page where new language ideas can be submitted.. https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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sphinx-vhdl: Automatic generation of documentation from VHDL
See: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
- Include I/O ports using parameter
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Active Busy VHDL Discussion Groups?
You too can contribute to the next revision of VHDL at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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Why is verilog more popular?
The IEEE WG welcomes new participants - especially people like yourself who have some experience. Got a good idea, you can interact with the VHDL WG community here: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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Signed Type vs Integer Type
If you want to get involved with language updates, we now use git issues. See here: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
- VHDL Standards and You ...
amaranth
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Why are there only 3 languages for FPGA development?
He probably meant Amaranth.
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VRoom A high end RISC-V implementation
As an aside, the latest and active development of nMigen has been rebranded a few months ago to Amaranth and can be found here: https://github.com/amaranth-lang/amaranth . In case people googled nMigen and came to the repository that hasn't been updated in two years.
- NMigen – A Python toolbox for building complex digital hardware (FPGAs)
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Facts every web dev should know before they burn out and turn to painting
Hmm. A followup question: are there any cheats/hacks that would make it possible (if painful) to for example explore the world of USB3, PCIe, or Linux on low-end-ish ARM (eg https://www.thirtythreeforty.net/posts/2019/12/my-business-c..., based on the 533MHz https://linux-sunxi.org/F1C100s), without needing to buy equipment in the mid-4-figure/low-5-figure range, if I were able to substitute a statistically larger-than-average amount of free time (and discipline)?
For example, I learned about https://github.com/GlasgowEmbedded/glasgow recently, a bit of a niche kitchen sink that uses https://github.com/nmigen/nmigen/ to lower a domain-specific subset of Python 3 (https://nmigen.info/nmigen/latest/lang.html) into Verilog which then runs on the Glasgow board's iCE40HX8K. The project basically makes it easier to use cheap FPGAs for rapid iteration. (The README makes a point that the synthesis is sufficiently fast that caching isn't needed.)
In certain extremely specific situations where circumstances align perfectly (caveat emptor), devices like this can sometimes present a temporary escape to the inevitable process of acquiring one's first second-hand high-end oscilloscope (fingers-crossed the expensive bits still have a few years left in them). To some extent they may also commoditize the exploration of very high-speed interfaces, which are rapidly becoming a commonplace principal of computers (eg, having 10Gbps everywhere when USB3.1 hits market saturation will be interesting) faster than test and analysis kit can keep up (eg to do proper hardware security analysis work). The Glasgow is perhaps not quite an answer to that entire statement, but maybe represents beginning steps in that sort of direction.
So, to reiterate - it's probably an unhelpfully broad question, and I'm still learning about the field so haven't quite got the preciseness I want yet, but I'm curious what gadgetry, techniques, etc would perhaps allow someone to "hack it" and dive into this stuff on a shoestring budget? :)
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Awesome Lattice FPGA Boards
Worth knowing that are two "nmigen"s nowadays - the one originated in M-Labs and one under a project also called nmigen:
https://github.com/nmigen/nmigen
It's a fork, made for reasons, but more actively developed. whitequark (long time author/contributor) works on this fork, and no longer the M-Labs version.
- Chisel/Firrtl Hardware Compiler Framework
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Unifying the CUDA Python Ecosystem
Sounds like nmigen might be a good open source successor to the project that you describe: https://github.com/nmigen/nmigen
What are some alternatives?
sphinx-vhdl
SpinalHDL - Scala based HDL
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
chisel - Chisel: A Modern Hardware Design Language
chiselverify - A dynamic verification library for Chisel.
myhdl - The MyHDL development repository
pygears - HW Design: A Functional Approach
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
riscv-isa-manual - RISC-V Instruction Set Manual
glasgow - Scots Army Knife for electronics
cunumeric - An Aspiring Drop-In Replacement for NumPy at Scale