Toast-RV32i
Pipelined RISC-V RV32I Core in Verilog (by georgeyhere)
RISCV
A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i] (by georgeyhere)
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| Toast-RV32i | RISCV | |
|---|---|---|
| 2 | 1 | |
| 34 | 11 | |
| - | - | |
| 0.0 | 8.8 | |
| about 1 year ago | over 2 years ago | |
| C | C | |
| - | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Toast-RV32i
Posts with mentions or reviews of Toast-RV32i.
We have used some of these posts to build our list of alternatives
and similar projects.
- Intermediate FPGA project suggestions for resume
-
RV32i RISCV processor for resume - Suggestions/feedback?
Github: https://github.com/georgeyhere/Toast-RV32i
RISCV
Posts with mentions or reviews of RISCV.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-22.
-
Novice needs help with RISC-V toolchain
To this end, I wrote a testbench that encodes instructions and places them into a text file using SV structs. Is there any tool that can decode the output to Assembly instructions to check that the testbench is working? Or even better, is there some way to generate hex/binary code from Assembly? I have manually converted some instructions to binary and am reasonably sure the code works but am not 100% sure.
What are some alternatives?
When comparing Toast-RV32i and RISCV you can also consider the following projects:
riscv - RISC-V CPU Core (RV32IM)
spu32 - Small Processing Unit 32: A compact RV32I CPU written in Verilog
quasiSoC - No-MMU Linux capable RISC-V SoC designed to be useful.
bronzebeard - Minimal assembler and ecosystem for bare-metal RISC-V development
NyuziProcessor - GPGPU microprocessor architecture
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software