Surelog
slang
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Surelog
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Tracking mentions began in Dec 2020.
slang
- Is anyone aware of a commercial parser that converts modern system verilog, UVM, etc to JSON or YAML?
- Tools like Scitools Understand but support Verilog
- What cli tool can give me a list of input/ouput pins of my verilog modules?
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AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be Enabled by Xilinx Tech
Going to plug my work on this here: https://github.com/MikePopoloski/slang
At some point I'd like to see it integrated as the frontend to tools like Yosys to get best-in-class SystemVerilog support in open tools.
What are some alternatives?
verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
cudf - cuDF - GPU DataFrame Library
iverilog - Icarus Verilog
verilator - Verilator open-source SystemVerilog simulator and lint system
json - A C++11 library for parsing and serializing JSON to and from a DOM container in memory.
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
veridian - A SystemVerilog Language Server