SDRAM_Controller_Verilog
OpenROAD
| SDRAM_Controller_Verilog | OpenROAD | |
|---|---|---|
| - | 7 | |
| 4 | 1,328 | |
| - | 3.7% | |
| 0.0 | 10.0 | |
| about 3 years ago | 6 days ago | |
| Verilog | Verilog | |
| - | BSD 3-clause "New" or "Revised" License |
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SDRAM_Controller_Verilog
We haven't tracked posts mentioning SDRAM_Controller_Verilog yet.
Tracking mentions began in Dec 2020.
OpenROAD
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Importance of Open-Source EDA Tools for Academia
> [1]: https://theopenroadproject.org/
All it takes to check your point is to scroll down to the end and follow the link at the bottom of the page to the FOSSI foundation, who hosted this open letter, to realize that they have also developed some widely used EDA tools. Here's a link on case you have missed it
https://fossi-foundation.org/our-work/projects
- OpenROAD
- Ser programador científico en chile
- OpenROAD: Open IC Design Sythesis from Verilog
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I see that many open riscv cores use Scala that generate verilog. Is this common practice?
If you're interested in tools, I highly recommend going through the (Google-supported) OpenROAD toolset - these guys are building up a open-source infrastructure for the full digital flow: https://theopenroadproject.org/ .
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VLSI Tools
You can have a quick look at OpenROAD. It is open source but will take sometime to get started with.
What are some alternatives?
FPGA_SDRAM_Controller - SDRAM controller optimized to a memory bandwidth of 316MB/s
OpenROAD-flow-scripts - OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
siliconcompiler - A modular build system for hardware
XiangShan - Open-source high-performance RISC-V processor
chisel-template - A template project for beginning new Chisel work
hammer - Hammer: Highly Agile Masks Made Effortlessly from RTL
caravel_fulgor_opamp - Test Chip General Purpose OpAmp using Skywater SKY130 PDK
tcl-opencl - Tcl extension for OpenCL
OpenSource-RoadMap-DataScience - ¡Camino a una educación autodidacta en Ciencia de Datos!