SBusFPGA
Stuff to put a FPGA in a SBus system (SPARCstation) (by rdolbeau)
verilog-ethernet
Verilog Ethernet components for FPGA implementation (by alexforencich)
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| SBusFPGA | verilog-ethernet | |
|---|---|---|
| 5 | 32 | |
| 43 | 1,916 | |
| - | - | |
| 5.6 | 8.8 | |
| 7 months ago | about 2 months ago | |
| Python | Verilog | |
| GNU General Public License v3.0 or later | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
SBusFPGA
Posts with mentions or reviews of SBusFPGA.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-08-31.
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Sparcstation 20 NetBSD 9.3 playing some Amiga mod music
Also a VSIMM, guessing you're using the internal SX / cg14 for display ? 4 or 8 MiB ? 8 are near impossible to come by, and 4 are not much better... But they're the best way to get a truecolor display in a vintage Sun - the only one that can do some level of XRender acceleration (unless you roll your own, that is ;-) ).
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Desktop GPU + PCIe + MPsoc
In the middle you can try and design your own device and add support to whichever piece of software you need. It's an interesting exercise... (am here, doing that ;-) ).
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I want to get a computer I can understand, but I'm a millennial, what do I really want?
I might be biased though :-)
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
New peripherals on an expansion board for a SPARCstation (90's Sun workstation).
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SPARCstation 20 with FPGA-based 256 MiB DDR3 RAM disk & USB controller
Devices live on a custom-made SBus expansion board with an Artix-7 FPGA on it ; full project is open-source.
verilog-ethernet
Posts with mentions or reviews of verilog-ethernet.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-21.
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Quartus Tcl Build Script
Tcl, not sure, but I have done it with makefiles. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/C10LP/fpga.
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Using Si5324 as a clock generator on virtex-7 board
For that part I think you need to use the software from silicon labs (might be skyworks now) to generate the stuff you need to write to the registers. Then, you can use something like https://github.com/alexforencich/verilog-i2c/blob/master/rtl/i2c_init.v. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/HTG9200/fpga_10g for an example that targets the Si5341 specifically.
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DE2-115 Ethernet Network Setup
For a personal project I'm trying to send data via Ethernet from my laptop into the FPGA, where it has some filtering and other processing done to it, then back into my laptop. I've been trying to get this repo to work, but there's a problem: my ancient macbook can't run Quartus, so I need to use campus PCs to build the project and program the board, but I don't have permissions to successfully run the makefiles that build the project.
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ROS 2 Humble in AMD KR260 with Yocto
No there's none. Not in this post at least, but it certain is being used. If you're interested in that, follow my progress at https://github.com/alexforencich/verilog-ethernet/issues/146 (or stay tuned/reach out to Acceleration Robotics for early previews and support) for a 10G NIC on the KR260.
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Choice of LFSR When implementing the ARP Cache in a UDP Stack
So, im trying to understand the UDP implementation in verilog-ethernet. In particular I am looking into the ARP Cache and have a query.
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Preference for Combinational or Sequential design?
I've been studying u/alexforencich's ethernet library since I'm working on a similar project. I've been noting his interesting design style. When I think about a solution for a problem, I immediately naturally thing about a sequential design whereas he has tons of combination logic in his designs.
- Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
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Verilog Question- Setting a register concurrently twice in always block
I was studying Alex Forencich's FCS verilog and noticed the following always block:
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LiteX SGMII support
This repo support the VCU108 for a Verilog ethernet connection: https://github.com/alexforencich/verilog-ethernet
- Stream data into FPGA from PC
What are some alternatives?
When comparing SBusFPGA and verilog-ethernet you can also consider the following projects:
SpinalHDL - Scala based HDL
corundum - Open source FPGA-based NIC and platform for in-network compute
xfcp - Extensible FPGA control platform
litex - Build your hardware, easily!
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
embox - Modular and configurable OS for embedded applications
cocotbext-axi - AXI interface modules for Cocotb
FPGA_RealTime_and_Static_Sobel_Edge_Detection - Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
SBusFPGA vs SpinalHDL
verilog-ethernet vs corundum
SBusFPGA vs xfcp
verilog-ethernet vs litex
SBusFPGA vs litex
verilog-ethernet vs SpinalHDL
SBusFPGA vs satcat5
verilog-ethernet vs embox
SBusFPGA vs corundum
verilog-ethernet vs cocotbext-axi
SBusFPGA vs FPGA_RealTime_and_Static_Sobel_Edge_Detection
verilog-ethernet vs satcat5