SBusFPGA
satcat5
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SBusFPGA | satcat5 | |
---|---|---|
5 | 25 | |
43 | 387 | |
- | 36.7% | |
5.6 | 3.8 | |
7 months ago | about 2 months ago | |
Python | VHDL | |
GNU General Public License v3.0 or later | CERN Open Hardware Licence Version 2 - Weakly Reciprocal |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
SBusFPGA
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Sparcstation 20 NetBSD 9.3 playing some Amiga mod music
Also a VSIMM, guessing you're using the internal SX / cg14 for display ? 4 or 8 MiB ? 8 are near impossible to come by, and 4 are not much better... But they're the best way to get a truecolor display in a vintage Sun - the only one that can do some level of XRender acceleration (unless you roll your own, that is ;-) ).
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Desktop GPU + PCIe + MPsoc
In the middle you can try and design your own device and add support to whichever piece of software you need. It's an interesting exercise... (am here, doing that ;-) ).
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I want to get a computer I can understand, but I'm a millennial, what do I really want?
I might be biased though :-)
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
New peripherals on an expansion board for a SPARCstation (90's Sun workstation).
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SPARCstation 20 with FPGA-based 256 MiB DDR3 RAM disk & USB controller
Devices live on a custom-made SBus expansion board with an Artix-7 FPGA on it ; full project is open-source.
satcat5
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Layout of Rust's u128 and i128 changed
I needed 128-bit and 256-bit integers on an embedded project recently.
In short, it was for fixed-point digital signal processing. The raw input and output samples were int64_t. We needed to add, subtract, multiply, and accumulate these to do filtering and linear regression with no loss of precision.
Conventional bigintegers weren't an option because the target application doesn't allow heap allocation. So we rolled our own [1] stack-allocated, fixed-width big integer class.
[1] https://github.com/the-aerospace-corporation/satcat5/blob/ma...
- Show HN: SatCat5, the open-source FPGA Ethernet switch
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CRC32 algorithm match value between 96 bit wide data bus and 24 bit wide data bus
And here's an open-source implementation I wrote a few years back. You can skip the part at the end that handles variable-length trailing bytes, since you have a fixed-width input.
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Questions about lattice ecp5 fpga.
My SatCat5 project also has a few options. Anything under src/vhdl/common/cfgbus_* can be connected to AXI or Wishbone with a simple adapter.
- SatCat5: FPGA gateware that implements a low-power, mixed-media Ethernet switch
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GPSDO without VCXO?
For an all-digital solution, here's an NCO that generates an arbitrary-frequency square wave from a numeric counter.
- network switch
What are some alternatives?
SpinalHDL - Scala based HDL
verilog-ethernet - Verilog Ethernet components for FPGA implementation
xfcp - Extensible FPGA control platform
surf - A huge VHDL library for FPGA development
litex - Build your hardware, easily!
opentitan - OpenTitan: Open source silicon root of trust
corundum - Open source FPGA-based NIC and platform for in-network compute
chisel - Chisel: A Modern Hardware Design Language
FPGA_RealTime_and_Static_Sobel_Edge_Detection - Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
basejump_stl - BaseJump STL: A Standard Template Library for SystemVerilog