satcat5
basejump_stl
| satcat5 | basejump_stl | |
|---|---|---|
| 25 | 4 | |
| 390 | 447 | |
| 10.5% | 2.0% | |
| 3.8 | 6.2 | |
| 2 months ago | about 1 month ago | |
| VHDL | SystemVerilog | |
| CERN Open Hardware Licence Version 2 - Weakly Reciprocal | GNU General Public License v3.0 or later |
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satcat5
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Layout of Rust's u128 and i128 changed
I needed 128-bit and 256-bit integers on an embedded project recently.
In short, it was for fixed-point digital signal processing. The raw input and output samples were int64_t. We needed to add, subtract, multiply, and accumulate these to do filtering and linear regression with no loss of precision.
Conventional bigintegers weren't an option because the target application doesn't allow heap allocation. So we rolled our own [1] stack-allocated, fixed-width big integer class.
[1] https://github.com/the-aerospace-corporation/satcat5/blob/ma...
- Show HN: SatCat5, the open-source FPGA Ethernet switch
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CRC32 algorithm match value between 96 bit wide data bus and 24 bit wide data bus
And here's an open-source implementation I wrote a few years back. You can skip the part at the end that handles variable-length trailing bytes, since you have a fixed-width input.
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Questions about lattice ecp5 fpga.
My SatCat5 project also has a few options. Anything under src/vhdl/common/cfgbus_* can be connected to AXI or Wishbone with a simple adapter.
- SatCat5: FPGA gateware that implements a low-power, mixed-media Ethernet switch
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GPSDO without VCXO?
For an all-digital solution, here's an NCO that generates an arbitrary-frequency square wave from a numeric counter.
- network switch
basejump_stl
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Extra-wide aspect ratio FIFO in Vivado?
BaseJump STL ( https://github.com/bespoke-silicon-group/basejump_stl ) has lots of these plumbing modules, silicon-validated several times
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Cross module reference (XMR)?
It depends on your mapping algorithm and whether the tools you’re looking at supported mixed-language synthesis, but you can always use our battle-tested components for these kind of functions: https://github.com/bespoke-silicon-group/basejump_stl
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Any recommendations for an RTL "standard library"?
https://github.com/bespoke-silicon-group/basejump_stl maybe?
- Data flow ternary vs behavioral case statements
What are some alternatives?
verilog-ethernet - Verilog Ethernet components for FPGA implementation
chisel - Chisel: A Modern Hardware Design Language
SpinalHDL - Scala based HDL
opentitan - OpenTitan: Open source silicon root of trust
surf - A huge VHDL library for FPGA development
PipelineC - A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
tiny-cores - Collection of assorted small cores