NyuziProcessor
verilog-pcie
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| NyuziProcessor | verilog-pcie | |
|---|---|---|
| 10 | 8 | |
| 1,916 | 947 | |
| - | - | |
| 3.4 | 6.5 | |
| 4 days ago | 3 days ago | |
| C | Verilog | |
| Apache License 2.0 | MIT License |
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NyuziProcessor
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Tiny GPU: A minimal GPU implementation in Verilog
Nice! I warmly encourage open-core GPU work.
Here's another: https://github.com/jbush001/NyuziProcessor
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FuryGpu – Custom PCIe FPGA GPU
There's also Nyuzi which is more GPGPU focused https://github.com/jbush001/NyuziProcessor, but the author also experimented with having it do 3D graphics.
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The WeeCee – Tiny Vortex86-Based DOS Gaming PC
You could probably layer a software implementation of the rasterization pipeline on top of a compute-focused open-source GPU architecture like Nyuzi: https://github.com/jbush001/NyuziProcessor/
I would expect a 2x slowdown over hardware rasterization, based on NVIDIA's work on such an approach, but this is probably fine if you're just trying to match Voodoo3 performance. And one could imagine bolting a minimal hardware rasterizer on top of Nyuzi to speed things up once the software implementation is working.
- FPGA as a GPU for Linux
- Nyuzi – An Experimental Open-Source FPGA GPGPU Processor
- An Experimental (Open-Source FPGA) GPGPU Processor called Nyuzi (by @jbush001)
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Exploring RustFFT's SIMD Architecture
Sounds like the Nyuzi processor :D
verilog-pcie
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FuryGpu – Custom PCIe FPGA GPU
The GPU uses https://github.com/alexforencich/verilog-pcie + the Xilinx PCIe hard IP core. When using the device-independent DMA engine, that library supports both Xilinx and Intel FPGAs.
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Any good tips for writing IP that inputs/outputs AXI stream?
Most definitely. Most of my stuff still uses skid buffers, but I have been converting stuff here and there to use FIFOs, and this I think was one of the first ones I did this to: https://github.com/alexforencich/verilog-pcie/blob/master/rtl/dma_client_axis_source.v. The output FIFO is the last ~70 lines or so. This one doesn't really take that much advantage over the half full feedback. I think that's the case for the PCIe write DMA engine, but that's a much more complex module.
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FPGA Dev Live Stream: PCIe DMA on Stratix 10 MX
For reference, the new DMA interface module with the generic PCIe interface is here, and the shim for Xilinx UltraScale devices is here.
- How to reprogram FPGA without loosing PCIe connection
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What do these PCIe error messages mean? Getting these messages from custom embedded hardware, but PCIe still works fine...
Try https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_set_speed.sh
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PCIe Express on Artix-7 Board?
You need something a bit lower-level to trigger a reset and re-enumeration of the device. I put this script together for that on linux, definitely saves a lot of reboots when the PCIe configuration does not change: https://github.com/alexforencich/verilog-pcie/blob/master/scripts/pcie_hot_reset.sh . If you do change the BAR configuration or other PCIe IP core settings, a reboot is probably necessary.
What are some alternatives?
vdpau-va-driver-vp9 - Experimental VP9 codec support for vdpau-va-driver (NVIDIA VDPAU-VAAPI wrapper) and chromium-vaapi
dma_ip_drivers - Xilinx QDMA IP Drivers
openvga
nitefury-popr
TrellisBoard - Ultimate ECP5 development board
vgasim - A Video display simulator
hardware - Verilog development and verification project for HOL4
ao486_MiSTer - ao486 port for MiSTer
OpenSimplex2 - C implementation for CPU and GPU of OpenSimplex 2
JuicyPixels-stbir - Interface to STB Image Resize for the Haskell image library JuicyPixels
SummerCart64 - SummerCart64 - a fully open source Nintendo 64 flashcart
RISCV - A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]