NyuziProcessor
RISCV
Our great sponsors
| NyuziProcessor | RISCV | |
|---|---|---|
| 10 | 1 | |
| 1,916 | 11 | |
| - | - | |
| 3.4 | 8.8 | |
| 3 days ago | over 2 years ago | |
| C | C | |
| Apache License 2.0 | - |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
NyuziProcessor
-
Tiny GPU: A minimal GPU implementation in Verilog
Nice! I warmly encourage open-core GPU work.
Here's another: https://github.com/jbush001/NyuziProcessor
-
FuryGpu – Custom PCIe FPGA GPU
There's also Nyuzi which is more GPGPU focused https://github.com/jbush001/NyuziProcessor, but the author also experimented with having it do 3D graphics.
-
The WeeCee – Tiny Vortex86-Based DOS Gaming PC
You could probably layer a software implementation of the rasterization pipeline on top of a compute-focused open-source GPU architecture like Nyuzi: https://github.com/jbush001/NyuziProcessor/
I would expect a 2x slowdown over hardware rasterization, based on NVIDIA's work on such an approach, but this is probably fine if you're just trying to match Voodoo3 performance. And one could imagine bolting a minimal hardware rasterizer on top of Nyuzi to speed things up once the software implementation is working.
- FPGA as a GPU for Linux
- Nyuzi – An Experimental Open-Source FPGA GPGPU Processor
- An Experimental (Open-Source FPGA) GPGPU Processor called Nyuzi (by @jbush001)
-
Exploring RustFFT's SIMD Architecture
Sounds like the Nyuzi processor :D
RISCV
-
Novice needs help with RISC-V toolchain
To this end, I wrote a testbench that encodes instructions and places them into a text file using SV structs. Is there any tool that can decode the output to Assembly instructions to check that the testbench is working? Or even better, is there some way to generate hex/binary code from Assembly? I have manually converted some instructions to binary and am reasonably sure the code works but am not 100% sure.
What are some alternatives?
vdpau-va-driver-vp9 - Experimental VP9 codec support for vdpau-va-driver (NVIDIA VDPAU-VAAPI wrapper) and chromium-vaapi
spu32 - Small Processing Unit 32: A compact RV32I CPU written in Verilog
openvga
bronzebeard - Minimal assembler and ecosystem for bare-metal RISC-V development
TrellisBoard - Ultimate ECP5 development board
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
hardware - Verilog development and verification project for HOL4
quasiSoC - No-MMU Linux capable RISC-V SoC designed to be useful.
ao486_MiSTer - ao486 port for MiSTer
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
OpenSimplex2 - C implementation for CPU and GPU of OpenSimplex 2
JuicyPixels-stbir - Interface to STB Image Resize for the Haskell image library JuicyPixels