slang
Surelog
slang | Surelog | |
---|---|---|
4 | 1 | |
536 | 25 | |
- | - | |
9.7 | 9.4 | |
about 6 hours ago | 2 months ago | |
C++ | C++ | |
MIT License | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
slang
- Is anyone aware of a commercial parser that converts modern system verilog, UVM, etc to JSON or YAML?
- Tools like Scitools Understand but support Verilog
- What cli tool can give me a list of input/ouput pins of my verilog modules?
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AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be Enabled by Xilinx Tech
Going to plug my work on this here: https://github.com/MikePopoloski/slang
At some point I'd like to see it integrated as the frontend to tools like Yosys to get best-in-class SystemVerilog support in open tools.
Surelog
We haven't tracked posts mentioning Surelog yet.
Tracking mentions began in Dec 2020.
What are some alternatives?
verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
iverilog - Icarus Verilog
cudf - cuDF - GPU DataFrame Library
json - A C++11 library for parsing and serializing JSON to and from a DOM container in memory.
verilator - Verilator open-source SystemVerilog simulator and lint system
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
veridian - A SystemVerilog Language Server