Projects
picorv32
Projects | picorv32 | |
---|---|---|
7 | 16 | |
354 | 2,783 | |
- | 2.0% | |
5.2 | 5.2 | |
6 months ago | about 1 month ago | |
C++ | Verilog | |
- | ISC License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Projects
- Processor's microcode pipeline from die analysis
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Building a Frankenstein 64
Nice work and thanks for the writeup. Ted Fried has a variety of microsequencer based CPU cores based on FPGA (and ARM) and I think they are quite good.
https://microcorelabs.wordpress.com/2021/04/19/mcl64-worlds-...
https://github.com/MicroCoreLabs/Projects
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Show HN: Tenebra game PC port of popular Commodore 64 game
At that point you might as well go MCL64 Teensy replica https://microcorelabs.wordpress.com/2021/04/19/mcl64-worlds-...
"comparing the Super CPU accelerated to 20Mhz and the MCL64 in its accelerated mode, the MCL64 is roughly 2X faster than the Super CPU"
https://microcorelabs.wordpress.com/2021/04/16/mcl64-mos-651...
https://microcorelabs.wordpress.com/2021/03/14/mcl64-commodo...
Fully open source https://github.com/MicroCoreLabs/Projects/tree/master/MCL64
- Macintosh booting!
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Apple to Move a Part of Its Embedded Cores to RISC-V
There is a difference, but not much!
https://github.com/MicroCoreLabs/Projects/tree/master/MCL51
- ANNOUNCE: 68000 test cases
- What's everyone currently working on?
picorv32
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RISC-V support in Android just got a big setback
> Right now, most devices on the market do not support the C extension
This is not true and easily verifiable.
The C extension is defacto required, the only cores that don't support it are special purpose soft cores.
C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file
Supports M and C extensions https://github.com/YosysHQ/picorv32
Another sized optimized core with C extension support https://github.com/lowrisc/ibex
C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html
This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax
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SPI PROTOCOL in FPGA
In contrast to most people here saying you NEED to spend money. I disagree with that. You can implement and simulate a SPI master/slave fully on your computer, no FPGA or other hardware required. There are simulation models for SPI peripherals you could use. For example: https://github.com/YosysHQ/picorv32/blob/master/picosoc/spiflash.v
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How many gates does a decent risc-v implementation take?
The Pico RV32 is pretty small, and can go as low as about 750 LUTs, with most features elided. I don't know how Xilinix LUTs translate to Lattice though.
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Open-source RISC-V CPU projects for contribution
Picorv32: https://github.com/YosysHQ/picorv32
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We ran a Unix-like OS (Xv6) on our home-built CPU with our home-built C compiler
There are loads of free RISC-V cores that you can read the source of and run on cheap FPGAs. Take a look at PicoRV32: https://github.com/YosysHQ/picorv32
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
picorv32 is written in Verilog.
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
That is, reducing the number of LUT required to implement a CPU of a given ISA.
A basic RV32 CPU is down to 500-700 LUT.
https://github.com/YosysHQ/picorv32
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Designing a reasonable memory interface
I've bought a cheap FPGA board (Sipeed Tang Nano 9K) because I want to implement a little 8 or 16-bit CPU. The FPGA has plenty of BRAM for such a little CPU, so I wouldn't even need to implement an SPI controller initially, but I want to implement a von Neumann architecture, and was wondering if the only way of doing so using single port (or semi dual port) RAM would be to use 2 cycles or more for memory transfer operations (one for loading the instruction, one for executing the actual memory transfer), or if there was any technique that could be used to avoid this without having to implement instruction-level parallelism. Even if not, references to understandable code implementing a simple memory interface would be appreciated. I looked at PicoRV32 but couldn't really understand its inner workings.
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Risc-v rv32i softcore processor for Zybo-z7-10
Have you looked at PicoRV32? https://github.com/YosysHQ/picorv32
What are some alternatives?
decaf-emu - Researching Wii U emulation.
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
XTulator - XTulator is a portable, open source x86 PC emulator currently supporting the 8086 instruction set and 80186 extensions.
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
temu-vsb - TEMU ("Tandy Emulator") and VSB ("Virtual Sound Blaster"), two nifty MS-DOS TSR utilities originally developed by Andrew Zabolotny (Андрей Заболотный).
rocket-chip - Rocket Chip Generator
gba-tests - A collection of Game Boy Advance tests.
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
SNES - SNES Assembly Programming
wd65c02 - Cycle accurate FPGA implementation of various 6502 CPU variants
PSX - PlayStation Bare Metal Mips Assembly Programming
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro