Hastlayer-SDK
Turning .NET software into FPGA hardware for faster execution and lower power usage. (by Lombiq)
fpu-sp
IEEE 754 floating point library in system-verilog and vhdl (by taneroksuz)
Hastlayer-SDK | fpu-sp | |
---|---|---|
1 | 3 | |
295 | 21 | |
1.0% | - | |
8.6 | 6.8 | |
about 1 month ago | 7 days ago | |
VHDL | VHDL | |
BSD 3-clause "New" or "Revised" License | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Hastlayer-SDK
Posts with mentions or reviews of Hastlayer-SDK.
We have used some of these posts to build our list of alternatives
and similar projects.
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Demo of achieving hardware acceleration using .NET on cubesats to lower both the risks and costs
Interesting demo of Turning .NET assemblies into FPGA hardware for faster execution and lower power usage using an open source framework.
fpu-sp
Posts with mentions or reviews of fpu-sp.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-14.
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Intel discontinues Nios II IP
My team has a solution in place already, which was to write all of our floating point code to call macros rather than putting arithmetic in the code. This allowed us to port easily to an RV32IM CPU (a fork of this one) then memory map an FPU onto it, the macros were then changed to atomically access the FPU registers for any floating point arithmetic. In Intel chips we are using the Nios II floating point hardware 2 (which can be instantiated separately), in other vendors we use a combination of operators from the Opencores FPU and this one, depending upon what operators are selected via generics, the maths library will pick up what configuration is used and choose the available operators.
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High level floating point arithmetic in vhdl
Another really nice one that I found recently, uses a fused multiply add unit rather than seperate multiplier and adder. It's available in both mixed precision (double/single) and single precision flavours.
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Got any good reads on floating point math design?
I recently saw an interesting idea in this VHDL repository which combines addition and multiplication in a single fused multiply add unit. Division and square root are combined as well. In my opinion the FMADD block needs some more pipeline stages.
What are some alternatives?
When comparing Hastlayer-SDK and fpu-sp you can also consider the following projects:
fpu - IEEE 754 floating point library in system-verilog and vhdl
cvfpu - Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Arcade_Galaga - Galaga Arcade Core
sdram-fpga - A FPGA core for a simple SDRAM controller.
mrisc32-a1 - A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA