Hastlayer-SDK
sdram-fpga
Hastlayer-SDK | sdram-fpga | |
---|---|---|
1 | 2 | |
295 | 107 | |
1.0% | - | |
8.6 | 10.0 | |
about 1 month ago | over 2 years ago | |
VHDL | VHDL | |
BSD 3-clause "New" or "Revised" License | MIT License |
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Hastlayer-SDK
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Demo of achieving hardware acceleration using .NET on cubesats to lower both the risks and costs
Interesting demo of Turning .NET assemblies into FPGA hardware for faster execution and lower power usage using an open source framework.
sdram-fpga
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Seeking Help with SDRAM Controller Debugging
Initially, I attempted to adapt an SDRAM [controller project I found on GitHub]( https://github.com/nullobject/sdram-fpga/blob/master/sdram.vhd) to my board by configuring the necessary parameters such as timing constants and memory dimensions.
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SDRAM clock vs controller clock vs system clock
here you go
What are some alternatives?
fpu-sp - IEEE 754 floating point library in system-verilog and vhdl
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
fpu - IEEE 754 floating point library in system-verilog and vhdl
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
Arcade_Galaga - Galaga Arcade Core
uart-for-fpga - Simple UART controller for FPGA written in VHDL
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
pico-png - PNG encoder, implemented in VHDL
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
pocket-cnn - CNN-to-FPGA-framework for small CNN, written in VHDL and Python
wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).