FPGA_RealTime_and_Static_Sobel_Edge_Detection
Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images (by AngeloJacobo)
BYU_PYNQ_PR_Video_Pipeline_Hardware
BYU Pynq PR Video Pipeline Hardware (by byuccl)
| FPGA_RealTime_and_Static_Sobel_Edge_Detection | BYU_PYNQ_PR_Video_Pipeline_Hardware | |
|---|---|---|
| 3 | 2 | |
| 36 | 7 | |
| - | - | |
| 0.0 | 0.0 | |
| over 2 years ago | over 4 years ago | |
| Verilog | VHDL | |
| MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
FPGA_RealTime_and_Static_Sobel_Edge_Detection
Posts with mentions or reviews of FPGA_RealTime_and_Static_Sobel_Edge_Detection.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-09.
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Sobel edge detection
Hi, you might be interested on having a look at this project. The main RTL for the convolution is in sobel_convolution.v
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
I posted this project on this sub three weeks ago,
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Real-Time Sobel Edge Detection using FPGA (repo link in the comments)
Project repository
BYU_PYNQ_PR_Video_Pipeline_Hardware
Posts with mentions or reviews of BYU_PYNQ_PR_Video_Pipeline_Hardware.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-11-15.
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References for video system design on FPGAs.
Here is my example: Thesis: https://scholarsarchive.byu.edu/etd/8620/ HW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline_Hardware SW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
What are some alternatives?
When comparing FPGA_RealTime_and_Static_Sobel_Edge_Detection and BYU_PYNQ_PR_Video_Pipeline_Hardware you can also consider the following projects:
litex - Build your hardware, easily!
verilog-ethernet - Verilog Ethernet components for FPGA implementation
SpinalHDL - Scala based HDL
WARP_Core - Wilson AXI RISCV Processor Core
FPGA_OV7670_Camera_Interface - Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
verilog-wishbone - Verilog wishbone components
ULX3S_FPGA_Camera_Streaming - Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs litex
BYU_PYNQ_PR_Video_Pipeline_Hardware vs verilog-ethernet
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs SpinalHDL
BYU_PYNQ_PR_Video_Pipeline_Hardware vs SpinalHDL
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs verilog-ethernet
BYU_PYNQ_PR_Video_Pipeline_Hardware vs WARP_Core
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs FPGA_OV7670_Camera_Interface
BYU_PYNQ_PR_Video_Pipeline_Hardware vs SBusFPGA
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs SBusFPGA
BYU_PYNQ_PR_Video_Pipeline_Hardware vs verilog-wishbone
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs ULX3S_FPGA_Camera_Streaming
BYU_PYNQ_PR_Video_Pipeline_Hardware vs satcat5