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Top 6 Uvm Open-Source Projects
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cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
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InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
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Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX (by chipsalliance)
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open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
The use of cocotb and pyuvm for verification
NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
Uvm related posts
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Designing a Low Latency 10G Ethernet Core
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Use cocotb to test and verify chip designs in Python
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Help understanding how this makefile works?
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COBS protocol decoder progress
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RgGen v0.28.0
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AXI-Stream meme
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cocotb
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A note from our sponsor - InfluxDB
www.influxdata.com | 11 May 2024
Index
What are some of the best open-source Uvm projects? This list will help you:
Project | Stars | |
---|---|---|
1 | cocotb | 1,614 |
2 | uvm | 503 |
3 | Surelog | 331 |
4 | rggen | 280 |
5 | open-register-design-tool | 182 |
6 | PeakRDL-uvm | 45 |
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