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skywater-pdk
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open-register-design-tool
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PeakRDL-uvm discussion
PeakRDL-uvm reviews and mentions
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PeakRDL-Regblock: A free & open source tool that generates SystemVerilog control & status registers (CSR) from SystemRDL
If you're interested register automation, be sure to check out some of my other projects: * systemrdl-compiler * Compiler front-end for the SystemRDL 2.0 language. Want to generate something yourself from SystemRDL input? No problem - use this language interpreter as your front-end. * PeakRDL-html * Generates dynamic and pretty looking HTML documentation * PeakRDL-ipxact * Import/export IP-XACT XML * PeakRDL-uvm * Generate a UVM register model * And a bunch of other random stuff under my SystemRDL GitHub project.
Stats
SystemRDL/PeakRDL-uvm is an open source project licensed under GNU General Public License v3.0 only which is an OSI approved license.
The primary programming language of PeakRDL-uvm is Python.