PeakRDL-uvm

Generate UVM register model from compiled SystemRDL input (by SystemRDL)

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better PeakRDL-uvm alternative or higher similarity.

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PeakRDL-uvm reviews and mentions

Posts with mentions or reviews of PeakRDL-uvm. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-03-20.
  • PeakRDL-Regblock: A free & open source tool that generates SystemVerilog control & status registers (CSR) from SystemRDL
    3 projects | /r/FPGA | 20 Mar 2022
    If you're interested register automation, be sure to check out some of my other projects: * systemrdl-compiler * Compiler front-end for the SystemRDL 2.0 language. Want to generate something yourself from SystemRDL input? No problem - use this language interpreter as your front-end. * PeakRDL-html * Generates dynamic and pretty looking HTML documentation * PeakRDL-ipxact * Import/export IP-XACT XML * PeakRDL-uvm * Generate a UVM register model * And a bunch of other random stuff under my SystemRDL GitHub project.

Stats

Basic PeakRDL-uvm repo stats
1
57
2.6
11 months ago

SystemRDL/PeakRDL-uvm is an open source project licensed under GNU General Public License v3.0 only which is an OSI approved license.

The primary programming language of PeakRDL-uvm is Python.


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