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At one point in time, I built my own AXI virtual FIFO. It wasn't all that hard to write, and took me about a weekend to write and verify. A lot of the things I complain about with AXI were simplified by the nature of the problem: I could insist, for example, that all bursts would be full length and aligned, that WSTRB would always be all ones and so forth. Since that time, I haven't yet had the opportunity to try this FIFO in any applications yet. Unlike what others have said of Xilinx's design, my own version didn't have any artificial size limits--other than the size of the FIFO needed to be at least one burst in length, and a power of two number of words. Neither did I keep track of TLAST or TKEEP. This essentially removed all packet boundaries--which may or may not work for your application.
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