Advice for studying the AXI specification

• wb2axip

  51 431 3.1 Verilog

  Bus bridges and other odds and ends

Some things to know: 1. Xilinx's example AXI designs are broken. Even their AXI Stream master is broken. Don't start there. 2. As others have suggested, starting with the AXI stream protocol, and learning AXI handshaking is a good place to start. This is where you'll find the bug in Xilinx's AXI stream master demo--in the handshaking. 2. Once you understand AXI handshaking, I'd then recommend learning about skidbuffers. Without them, you'll never get any decent throughput. 3. The next place I'd go would be to look into AXI-lite. Beware of backpressure! It has caused Xilinx no end of headaches, and forms the backdrop for many of the bugs in their example designs. If you want a working example design, check out this example design that I often use myself when working with AXI-lite. 4. For most use cases, you can stop here. For most of the things that need the full AXI specification for, you can already find example or vendor designs that'll work. (DMA's, MM2S, S2MM, virtual FIFO, video frame buffer reading, video frame buffer writing, etc.) 4. Once you've mastered AXI-lite, then it's time to understand AXI addressing, and the various FIX, WRAP, and INCR addressing modes and how the SIZE field impacts them. You'll need to understand this before diving into building your first AXI slave. Indeed, I've used the next AXI address module built and presented in that article in many designs--ASIC included. 5. The next step would be to build an fully capable AXI slave. 6. When it comes to AXI masters, I would similarly start with an AXI-Lite master. Technically, such a master should be able to be just as fast as an AXI full master. Practically and sadly, many designs cripple AXI-lite implementations. (Hello, Xilinx?) 7. A full discussion of AXI masters gets difficult. It's hard enough that I haven't (yet) posted on how to build general AXI masters--the addressing is just that hard to get right. (Usually takes me a couple of days.) However, you are welcome to examine some of those I've written and posted](https://zipcpu.com/blog/2021/06/28/master-examples.html) if you'd like. 8. I have posted about how to build an instruction fetch routine in both AXI-Lite, and then how to upgrade it to AXI (full). This goes over the AXI Exclusive access protocol, and how you can build a master that uses it--although I only really know of CPUs that need this protocol. 9. It's also important to know how to measure AXI performance. Just what kind of performance are you achieving, what is possible, and what can you expect are all good questions you'll want to know how to answer.

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