How to simulate Verilog designs REALLY quickly ?

• chisel

  25 3,708 9.7 Scala

  Chisel: A Modern Hardware Design Language (by chipsalliance)

  

As for now, we were using Chisel3 but it is not fast enough, and we are getting into more complicated designs (surch as RISC V). The webapp is slowly becoming unresponsive and unusable.

• cocotb

  28 1,599 9.7 Python

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  

I heard about Verilator but it is quite something to learn and I am not sure if its the proper tool for my needs. I have looked into cocotb, but it does not work really well on my side. Could you guys recommend me anything ?

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• signalflip-js

  3 16 0.0 C++

  verilator testbench w/ Javascript using N-API

I made a package called signalflip-js which would be good fit especially for a web app. It wraps the verilator testbench with javascript. An interesting thing to try here would be to compile verilator to wasm and use the wasm binary. DM me if you pick this route and need help

• signalflip-verilator-webapp

  1 0 0.0 Makefile

  A web app showing a example counter systemverilog design with testbench written in signalflip-js using Verilator as a simulator

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