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I've been doing several experiments to see if I can measure AXI4 latency and throughput. The measurement IP I'm using is posted here. It's got an AXI4-lite slave control port, together with an AXI4 full monitor port. Once you write a "start" signal to the AXI4-lite slave port, the core starts calculating statistics regarding the AXI4 full port. The statistics themselves are described in the documentation at the top of the file. From these, the core is designed to be able to measure both read and write latencies.
My current test case involves a ZipCPU and memory running Dhrystone. All but the Dhrystone software (that also drives the performance monitor and reads back and interprets the results) are posted on line, in case you want to see how I hooked it up.
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