Kite VS qtrvsim

Compare Kite vs qtrvsim and see what are their differences.

Kite

Kite: Architecture Simulator for RISC-V Instruction Set (by yonseicasl)
risc-v Simulator Architecture five-stage Pipeline Model Education Assembly computer-architecture microarchitecture pipelining branch-prediction Cache instruction-set instruction-set-architecture Memory instruction-dependency
Source Code
casl.yonsei.ac.kr
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qtrvsim

RISC-V CPU simulator for education purposes (by cvut)
risc-v cpu-emulator Teaching computer-architecture
Source Code
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Kite qtrvsim
1 1
14 422
- 6.4%
5.8 8.9
about 2 months ago 7 days ago
C++ C++
GNU General Public License v3.0 or later GNU General Public License v3.0 only
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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Kite

Posts with mentions or reviews of Kite. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-05-13.

qtrvsim

Posts with mentions or reviews of qtrvsim. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-01-26.
  • How a CPU works: Bare metal C on my RISC-V toy CPU
    4 projects | news.ycombinator.com | 26 Jan 2023
    - source & native releases: https://github.com/cvut/qtrvsim

    It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.

    I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu

What are some alternatives?

When comparing Kite and qtrvsim you can also consider the following projects:

rars - RARS -- RISC-V Assembler and Runtime Simulator

Astro8-Computer - Custom 16-bit homebrew CPU, emulator, renderer, circuit, and language

RISC-V-Guide - RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

fpga-experiments

lpub3d - An LDraw™ editor for LEGO® style digital building instructions.

cs2410 - An out-of-order execution CPU simulator for CS2410 Computer Architecture course final project at the University of Pittsburgh.

Ripes - A graphical processor simulator and assembly editor for the RISC-V ISA

risc-v_pipelined_cpu - RISC-V CPU with a 5-stage pipeline, written in SystemVerilog

rvalp - RISC-V Assembly Language Programming

Digital - A digital logic designer and circuit simulator.

peakperf - Achieve peak performance on x86 CPUs and NVIDIA GPUs

Kite vs rars qtrvsim vs Astro8-Computer Kite vs RISC-V-Guide qtrvsim vs fpga-experiments Kite vs lpub3d qtrvsim vs cs2410 Kite vs Ripes qtrvsim vs risc-v_pipelined_cpu Kite vs rvalp qtrvsim vs Digital Kite vs peakperf qtrvsim vs Ripes