vhdl-axis-uart
UART to AXI Stream interface written in VHDL (by fcayci)
surf
A huge VHDL library for FPGA development (by slaclab)
| vhdl-axis-uart | surf | |
|---|---|---|
| 2 | 1 | |
| 15 | 285 | |
| - | 1.1% | |
| 0.0 | 8.7 | |
| over 1 year ago | 7 days ago | |
| VHDL | VHDL | |
| MIT License | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
vhdl-axis-uart
Posts with mentions or reviews of vhdl-axis-uart.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-01-06.
- Understanding Serial port and transmission?
-
MIL-STD-1553 Implementation
not much different than something like this: https://github.com/fcayci/vhdl-axis-uart/blob/master/rtl/uart_rx.vhd
surf
Posts with mentions or reviews of surf.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-11-18.
What are some alternatives?
When comparing vhdl-axis-uart and surf you can also consider the following projects:
mil1553-spi - MIL-STD-1553 <-> SPI bridge
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
chisel - Chisel: A Modern Hardware Design Language
tiny-cores - Collection of assorted small cores
basejump_stl - BaseJump STL: A Standard Template Library for SystemVerilog
fusesoc-cores - FuseSoC standard core library
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
opentitan - OpenTitan: Open source silicon root of trust